ASAHI KASEI
[AK4644]
3. PLL Slave Mode (MCKI pin)
Example:
Audio I/F Format: MSB justified (ADC & DAC)
Input Master Clock Select at PLL Mode: 11.2896MHz
MCKO: Enable
Sampling Frequency: 44.1kHz
Power Supply
(1) Power Supply & PDN pin = “L” Æ “H”
(1)
PDN pin
(2)
(3)
PMVCM bit
(Addr:00H, D6)
(2)Addr:04H, Data:4AH
Addr:05H, Data:27H
(4)
MCKO bit
(Addr:01H, D1)
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:03H
MCKO output start
PMPLL bit
(Addr:01H, D0)
(5)
MCKI pin
Input
40msec(max)
(6)
MCKO pin
(7)
Output
Input
(8)
BICK and LRCK input start
BICK pin
LRCK pin
Figure 76. Clock Set Up Sequence (3)
<Example>
(1) After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK4644.
(2) DIF1-0, PLL3-0 and FS3-0 bits should be set during this period.
(3) Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM should first be powered up before the other block operates.
(4) Enable MCKO output: MCKO bit = “1”
(5) PLL starts after that the PMPLL bit changes from “0” to “1” and PLL reference clock (MCKI pin) is supplied.
PLL lock time is 40ms(max).
(6) The normal clock is output from MCKO after PLL is locked.
(7) The invalid frequency is output from MCKO during this period.
(8) BICK and LRCK clocks should be synchronized with MCKO clock.
MS0477-E-01
2006/10
- 85 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
