ASAHI KASEI
[AK4644]
3. Example of ALC Operation
Table 35 shows the examples of the ALC setting for mic recording.
fs=8kHz
Operation
fs=44.1kHz
Operation
Register Name Comment
Data
Data
01
0
LMTH1-0
ZELMN
ZTM1-0
Limiter detection Level
01
0
01
−4.1dBFS
Enable
32ms
−4.1dBFS
Enable
23.2ms
Limiter zero crossing detection
Zero crossing timeout period
Recovery waiting period
11
WTM2-0
*WTM2-0 bits should be the same or
longer data as ZTM1-0 bits.
Maximum gain at recovery operation
001
32ms
011
23.2ms
REF7-0
IVL7-0,
IVR7-0
E1H
E1H
+30dB
+30dB
E1H
E1H
+30dB
+30dB
Gain of IVOL
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Limiter ATT step
Recovery GAIN step
Fast Recovery Speed
ALC enable
00
00
00
1
1 step
1 step
4 times
Enable
00
00
00
1
1 step
1 step
4 times
Enable
Table 35. Example of the ALC setting
The following registers should not be changed during the ALC operation. These bits should be changed after the ALC
operation is finished by ALC bit = “0” or PMADL=PMADR bits = “0”.
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Zero Crossing Timeout Period = 32ms@8kHz
Limiter and Recovery Step = 1
Fast Recovery Speed = 4 step
Gain of IVOL = +30dB
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
Manual Mode
ALC bit = “1”
WR (ZTM1-0, WTM2-0, RFST1-0)
WR (REF7-0)
(1) Addr=06H, Data=14H
(2) Addr=08H, Data=E1H
(3) Addr=09H&0CH, Data=E1H
* The value of IVOL should be
the same or smaller than REF’s
WR (IVL/R7-0)
WR (RGAIN1, LMTH1)
(4) Addr=0BH, Data=00H
(5) Addr=07H, Data=21H
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
ALC Operation
Note : WR : Write
Figure 36. Registers set-up sequence at ALC operation
MS0477-E-01
2006/10
- 45 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
