ASAHI KASEI
[AK4644]
ALC Operation
The ALC (Automatic Level Control) is done by ALC block when ALC bit is “1”. When only DAC is powered-up, ALC
circuit operates at playback path. When only ADC is powered-up or both ADC and DAC are powered-up, ALC circuit
operates at recording path.
PMADL bit, PMADR bit PMDAC bit LOOP bit
Status
Power-down
Playback
ALC
0
1
0
x
x
x
0
1
Power-down
Playback path
Recording path
Recording path
Recording path
Default
“00”
Recording
Recording & Playback
Recording Monitor Playback
“01”, “10” or “11”
1
Table 27. ALC Setting (x: Don’t care)
1. ALC Limiter Operation
During the ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 28), the IVL
and IVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 29).
When ZELMN bit = “0” (zero cross detection is enabled), the IVL and IVR values are changed by ALC limiter operation
at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero crossing
timeout period of both ALC limiter and recovery operation (Table 30).
When ZELMN bit = “1” (zero cross detection is disabled), IVL and IVR values are immediately (period: 1/fs) changed by
ALC limiter operation. Attenuation step is fixed to 1 step regardless as the setting of LMAT1-0 bits.
The attenuation operation is done continuously until the input signal level becomes ALC limiter detection level (Table 28)
or less. After completing the attenuation operation, unless ALC bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTH1-0 bits.
LMTH1 LMTH0 ALC Limier Detection Level
ALC Recovery Waiting Counter Reset Level
−2.5dBFS > ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
0
0
1
1
0
1
0
1
Default
ALC Output ≥ −2.5dBFS
ALC Output ≥ −4.1dBFS
ALC Output ≥ −6.0dBFS
ALC Output ≥ −8.5dBFS
Table 28. ALC Limiter Detection Level / Recovery Counter Reset Level
ZELMN
LMAT1
LMAT0
ALC Limiter ATT Step
0
0
1
1
x
0
1
0
1
x
1 step
2 step
4 step
8 step
1step
0.375dB
0.750dB
1.500dB
3.000dB
0.375dB
Default
0
1
Table 29. ALC Limiter ATT Step (x: Don’t care)
Zero Crossing Timeout Period
ZTM1
ZTM0
8kHz
16ms
32ms
64ms
128ms
16kHz
8ms
16ms
32ms
64ms
44.1kHz
2.9ms
5.8ms
11.6ms
23.2ms
0
0
1
1
0
1
0
1
128/fs
256/fs
512/fs
1024/fs
Default
Table 30. ALC Zero Crossing Timeout Period
MS0477-E-01
2006/10
- 42 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
