[AK4634]
< MIC differential Input >
Dynamic SPK
R1, R2: Short
ZD1, ZD2: Open
Piezo SPK
R1, R2: ≥10Ω
ZD1, ZD2: Required
0.1µ
10
R1
Speaker
0.1µ
R2
ZD2
ZD1
I2C
DVDD
VSS2
SPN
VSS3
SVDD
AOUT
MPI
NC
1µ
220
SDTO
BICK
FCK
MCKO
SDTI
SPP
MICN
MICP
VCOC
TST3
1µ
1k
DSP
&
20 k
MCKI
1k
Top View
µP
CCLK
CSN
CDTI
TST2
VSS1
1µ
+
2.2µ
0.1µ
PDN
VCOM
AVDD
Rp
Cp
TST1
0.1µ
Analog Supply
+
10µ
2.2∼3.6V
Figure 58. Typical Connection Diagram
Notes:
- VSS1, VSS2 and VSS3 of the AK4634 should be distributed separately from the ground of external controllers.
- All digital input pins except pull-down pin should not be left floating.
- In EXT mode (PMPLL bit = “0”), Rp and Cp of the VCOC pin can be open.
- In PLL mode (PMPLL bit = “1”), Rp and Cp of the VCOC pin should be connected as shown in Table 45.
- When the AK4634 is used at master mode, FCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, a pull-up resistor with around 100Ω should be connected to LRCK and BICK pins of the AK4634.
-When AVDD, DVDD and SVDD were distributed, DVDD = 1.6 ~ 3.6 V, SVDD = 2.2 ~ 4.0 V.
Rp and Cp of
VCOC pin
PLL Lock
Time (max)
PLL3 PLL2 PLL1 PLL0 PLL Reference
Mode
Input Frequency
bit
bit
bit
bit
Clock Input Pin
Cp[F]
Rp[Ω]
6.8k
10k
10k
10k
10k
10k
10k
10k
0
1
2
3
6
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
1
1
1
1
0
0
0
1
0
1
0
1
0
1
FCK pin
BICK pin
BICK pin
BICK pin
MCKI pin
MCKI pin
MCKI pin
MCKI pin
N/A
1fs
16fs
32fs
220n
4.7n
4.7n
4.7n
4.7n
4.7n
10n
160ms
2ms
2ms
(default)
64fs
2ms
12MHz
24MHz
13.5MHz
27MHz
30ms
30ms
30ms
30ms
7
12
13
Others
10n
Others
Table 45. Setting of PLL Mode (*fs: Sampling Frequency, N/A: Not available)
Rev. 0.5
2007/10
- 74 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
