[AK4634]
SYSTEM DESIGN
Figure 57 and Figure 58 show the system connection diagram. The evaluation board [AKD4634] demonstrates the
optimum layout, power supply arrangements and measurement results.
< MIC Single-end Input >
Dynamic SPK
R1, R2: Short
ZD1, ZD2: Open
Piezo SPK
0.1µ
R1, R2: ≥10Ω
ZD1, ZD2: Required
10
R1
R2
Speaker
0.1µ
ZD2
ZD1
I2C
DVDD
VSS2
SPN
VSS3
SVDD
AOUT
MPI
NC
1µ
220
SDTO
BICK
FCK
MCKO
SDTI
CCLK
CSN
SPP
LIN
1µ
DSP
&
20 k
MCKI
2.2k
Top View
µP
CDTI
TST2
VSS1
MIC
1µ
+
2.2µ
0.1µ
PDN
VCOM
AVDD
VCOC
TST3
Rp
Cp
TST1
0.1µ
Analog Supply
+
10µ
2.2∼3.6V
Figure 57. Typical Connection Diagram
Notes:
- VSS1, VSS2 and VSS3 of the AK4634 should be distributed separately from the ground of external controllers.
- All digital input pins except pull-down pin should not be left floating.
- In EXT mode (PMPLL bit = “0”), Rp and Cp of the VCOC pin can be open.
- In PLL mode (PMPLL bit = “1”), Rp and Cp of the VCOC pin should be connected as shown in Table 45.
- When the AK4634 is used at master mode, FCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, a pull-up resistor with around 100Ω should be connected to LRCK and BICK pins of the AK4634.
-When AVDD, DVDD and SVDD were distributed, DVDD = 1.6 ~ 3.6 V, SVDD = 2.2 ~ 4.0 V.
Rev. 0.5
2007/10
- 73 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
