[AK4634]
(2) I2C-bus Control Mode (I2C pin = “H”)
The AK4634 supports the fast-mode I2C-bus (max: 400kHz). Pull-up resistors at SDA and SCL pins should be connected
to (DVDD+0.3)V or less voltage.
(2)-1. WRITE Operations
Figure 48 shows the data transfer sequence for the I2C-bus mode. All commands are preceded by a START condition. A
HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START condition (Figure 54). After the
START condition, a slave address is sent. This address is 7 bits long followed by the eighth bit that is a data direction bit
(R/W). The most significant seven bits of the slave address are fixed as “0010010” (Figure 49). If the slave address
matches that of the AK4634, the AK4634 generates an acknowledge and the operation is executed. The master must
generate the acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
(Figure 55). A R/W bit value of “1” indicates that the read operation is to be executed. A “0” indicates that the write
operation is to be executed.
The second byte consists of the control register address of the AK4634. The format is MSB first, and those most
significant 1-bits are fixed to zeros (Figure 50). The data after the second byte contains control data. The format is MSB
first, 8bits (Figure 51). The AK4634 generates an acknowledge after each byte is received. A data transfer is always
terminated by a STOP condition generated by the master. A LOW to HIGH transition on the SDA line while SCL is
HIGH defines a STOP condition (Figure 54).
The AK4634 can perform more than one byte write operation per sequence. After receipt of the third byte the AK4634
generates an acknowledge and awaits the next data. The master can transmit more than one byte instead of terminating the
write cycle after the first data byte is transferred. After receiving each data packet the internal 6-bit address counter is
incremented by one, and the next data is automatically taken into the next address. If the address exceeds 4FH prior to
generating a stop condition, the address counter will “roll over” to 00H and the previous data will be overwritten.
The data on the SDA line must remain stable during the HIGH period of the clock. The HIGH or LOW state of the data
line can only change when the clock signal on the SCL line is LOW (Figure 56) except for the START and STOP
conditions.
S
S
T
O
P
T
A
R
T
R/W="0"
Slave
Address
Sub
Address(n)
S
Data(n)
Data(n+1)
Data(n+x)
P
SDA
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Figure 48. Data Transfer Sequence at the I2C-Bus Mode
0
0
0
1
0
0
1
0
R/W
A0
Figure 49. The First Byte
A6
D6
A5
A4
A3
A2
D2
A1
D1
Figure 50. The Second Byte
D7
D5
D4
D3
D0
Figure 51. Byte Structure after the second byte
Rev. 0.5
2007/10
- 57 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
