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AK4613EQ 参数 Datasheet PDF下载

AK4613EQ图片预览
型号: AK4613EQ
PDF下载: 下载PDF文件 查看货源
内容描述: 4/12通道音频编解码器 [4/12-Channel Audio CODEC]
分类和应用: 解码器编解码器消费电路商用集成电路
文件页数/大小: 69 页 / 1130 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK4613]  
DAC Analog Output Characteristics (differential outputs)  
S/(N+D)  
fs=48kHz  
BW=20kHz  
0dBFS  
-60dBFS  
0dBFS  
90  
88  
100  
45  
98  
dB  
fs=96kHz  
BW=40kHz  
-60dBFS  
0dBFS  
-60dBFS  
42  
98  
42  
fs=192kHz  
BW=40kHz  
DR  
S/N  
(-60dBFS with A-weighted)  
(A-weighted)  
100  
100  
90  
108  
108  
110  
0
dB  
dB  
dB  
dB  
Interchannel Isolation  
Interchannel Gain Mismatch  
Gain Drift  
0.5  
-
20  
ppm/°C  
Output Voltage  
Load Resistance  
Load Capacitance  
Power Supply Rejection  
AOUT=0.63xVREFH2 (Note 8)  
(Note 10)  
±1.87  
2
±2.08  
±2.29  
Vpp  
kΩ  
pF  
dB  
30  
(Note 7)  
50  
Note 7. PSR is applied to AVDD1, AVDD2, DVDD, TVDD1 and TVDD2 with 1kHz, 50mVpp. VREFH1 and VREFH2  
pins are held a constant voltage +3.3V.  
Note 8. This value is (LIN+) – (LIN-) and (RIN+) – (RIN-). The voltage is proportional to VREFH1, VREFH2 voltage.  
Note 9. VREFH1 and VREFH2 are held +3.3V, the input bias voltage is set to AVDD1, 2 x 0.5. The 1kHz, 0.96Vpp  
signal is applied to LIN- and LIN+ with same phase (e.g. shorted) or RIN- and RIN+. The CMRR is measured as  
the attenuation level from 0dB = -7dBFS (since the normal 0.96Vpp = -7dBFS). This value is guaranteed but not  
tested.  
Note 10. For AC-load. In the case of DC-load is 5k.  
Note 11. This value is Load Capacitance for output pin to GND. In differential mode, this value should be estimated to be  
twice, because Load Capacitance exists to GND and between the differential pin.  
Parameter  
min  
typ  
max  
Units  
Power Supplies  
Power Supply Current  
Normal Operation (PDN pin = “H”)  
AVDD1+AVDD2  
DVDD  
fs=48kHz, 96kHz, 192kHz  
80.0  
14.0  
20.0  
33.0  
6.0  
125.0  
24.0  
35.0  
55.0  
8.0  
mA  
mA  
mA  
mA  
mA  
mA  
mA  
fs=48kHz  
fs=96kHz  
fs=192kHz  
fs=48kHz  
fs=96kHz  
fs=192kHz  
TVDD1+TVDD2  
Power-down mode  
7.0  
7.0  
9.5  
9.5  
(PDN pin = “L”, DVMPD = “ L”)  
AVDD1+AVDD2+DVDD+TVDD1+TVDD2  
(PDN pin = “L”, DVMPD = “ H”)  
(Note 12)  
(Note 12)  
300  
10  
550  
200  
µA  
µA  
AVDD1+AVDD2+DVDD+TVDD1+TVDD2  
Note 12. In the power-down mode, all digital input pins including clock pins are held VSS3 (TST1, TST3, TST4, TST5,  
CAD0, CAD1, I2C, CSN, CCLK, CDTI pins), VSS4 (TST2, M/S, MCKI, LRCK, BICK, SDTI1, SDTI2, SDTI3,  
SDTI4,SDTI5, SDTI6).  
MS1052-E-02  
2010/03  
- 11 -