ASAHI KASEI
[AK4564]
OPERATION OVERVIEW
n
System Clock
The clocks required to operate are MCLK (256fs/384fs), LRCK (fs) and BCLK (32fs~). The master clock (MCLK)
should be synchronized with LRCK. The phase between these clocks does not matter. The frequency of MCLK can be
input as 256fs or 384fs. When the 384fs is input, the internal master clock is divided into 2/3 automatically.
*fs is sampling frequency.
When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4564 may
occur click noise. DAC input data should be “0” to avoid click noise.
All external clocks (MCLK, BCLK and LRCK) should always be present except MIC = ADC = DAC = VCOM = HPP =
SPKP = AOUT1P = AOUT2P = “0” or PDN = “L”. If these clocks are not provided, the AK4564 may draw excess current
and will not operate properly because it utilizes these clocks for internal dynamic refresh of registers. If the external
clocks are not present, the AK4564 should be placed in MIC = ADC = DAC = VCOM = HPP = SPKP = AOUT1P =
AOUT2P = “0” or PDN = “L”. However, ADC, DAC and ALC2 are in power-down mode until MCLK, BCLK and
LRCK is input, even if they release a power-down mode by PDN pin or control register. (Refer to the “Power
Management Mode”.)
n System Reset
AK4564 should be reset once by bringing PDN pin “L” upon power-up. After the system reset operation, the all internal
registers become initial value.
Initializing cycle is 4128/fs=86ms@fs=48kHz. During initializing cycle, the ADC digital data outputs of both channels
are forced to a 2's compliment, “0”. Output data of ADC settles data equivalent for analog input signal after initializing
cycle. This cycle is not for DAC.
n Digital High Pass Filter
The AK4564 has a Digital High Pass Filter (HPF) to cancel DC-offset in ADC. The cut-off frequency of the HPF is 3.7Hz
at fs=48kHz and it is attenuated to –0.15dB at 20Hz. This cut-off frequency scales with the sampling frequency (fs).
MS0140-E-01
2002/07
- 14 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
