ASAHI KASEI
[AK4564]
DC CHARACTERISTICS
(Ta=25°C; AVDD, DVDD, SVDD=2.6 ~ 3.6V, MVDD, HVDD=2.6~ 5.5V)
Parameter
High-Level Input Voltage
Low-Level Input Voltage
High-Level Output Voltage
Low-Level Output Voltage
Input Leakage Current
Symbol
VIH
VIL
min
typ
max
-
0.6
-
0.2
±10
Units
V
V
1.5
-
-
-
-
-
-
Iout=-200mA
Iout=200mA
VOH
VOL
Iin
DVDD-0.2
V
V
-
-
mA
SWITCHING CHRACTERISTICS
(Ta=25°C; AVDD, DVDD, SVDD=2.6 ~ 3.6V, MVDD, HVDD=2.6~ 5.5V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing (MCLK)
256fs: Frequency
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
2.048
28
28
3.072
23
23
12.288
12.8
MHz
ns
ns
MHz
ns
ns
Pulse Width Low
Pulse Width High
384fs: Frequency
18.432
19.2
Pulse Width Low
Pulse Width High
LRCK Timing
Frequency
Duty Cycle
fs
Duty
8
45
48
50
50
55
kHz
%
Audio Interface Timing
BCLK Period
tBLK
tBLKL
tBLKH
tLRB
312.5
130
130
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
BCLK Pulse Width Low
Pulse Width High
LRCK Edge to BCLK “• ” (Note 31)
BCLK “• ” to LRCK Edge (Note 31)
LRCK to SDTO (MSB) Delay Time
BCLK “¯” to SDTO Delay Time
SDTI Latch Hold Time
SDTI Latch Set up Time
Control Interface Timing
CCLK Period
tBLR
50
tLRM
tBSD
tSDH
tSDS
80
80
50
50
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
200
80
80
50
50
150
50
50
ns
ns
ns
ns
ns
ns
ns
ns
CCLK Pulse Width Low
Pulse Width High
CDTI Latch Set up Time
CDTI Latch Hold Time
CSN “H” Time
CSN “¯” to CCLK “• ”
CCLK “• ” to CSN “• ”
Reset Timing
tCSH
PDN Pulse Width
PDN “• ” to SDTO Delay Time
tPDW
tPDV
150
ns
1/fs
4128
Note 31. BCLK rising edge must not occur at the same time as LRCK edge.
MS0140-E-01
2002/07
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
