ASAHI KASEI
[AK4562]
SWITCHING CHARACTERISTICS
(Ta=-20
∼
70°C; VA, VD=2.2
∼
3.0V, VT=1.8
∼
3.0V; C
L
=20pF)
Parameter
Symbol
min
Control Clock Frequency
Master Clock (MCLK)
256fs: Frequency
2.048
fCLK
Pulse Width Low
28
tCLKL
Pulse Width High
28
tCLKH
384fs: Frequency
3.072
fCLK
Pulse Width Low
23
tCLKL
Pulse Width High
23
tCLKH
Channel Clock (LRCK)
Frequency
8
fs
Duty Cycle
45
Audio Interface Timing
BCLK Period
312.5
tBLK
BCLK Pulse Width Low
130
tBLKL
Pulse Width High
130
tBLKH
-tBLKH+50
tBLR
BCLK “↓” to LRCK
tDLR
LRCK Edge to SDTO (MSB)
tDSS
BCLK “↓” to SDTO
50
tSDH
SDTI Hold Time
50
tSDS
SDTI Setup Time
Control Interface Timing (AKM)
CCLK Period
CCLK Pulse Width Low
Pulse Width High
CDATA Setup Time
CDATA Hold Time
CSN “H” Time
CSN “↓” to CCLK “↑”
CCLK “↑” to CSN “↑”
Control Interface Timing (SSB)
SCK Period
SCLK Pulse Width Low
Pulse Width High
SSI Setup Time
SSI Hold Time
Reset / Calibration Timing
PDN Pulse Width
PDN “↑” to SDTO
(Note 14)
tCCK
tCCKL
tCCKH
tCDS
tCDH
tCSW
tCSS
tCSH
tSCK
tSCKL
tSCKH
tSIS
tSIH
tPW
tPWV
200
80
80
50
50
150
50
50
250
100
100
50
50
150
4128
typ
max
Units
11.2896
12.8
16.9344
19.2
44.1
50
55
MHz
ns
ns
MHz
ns
ns
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/fs
tBLKL-50
80
80
Note : 14. These cycles are the numbers of LRCK rising from PDN pin rising.
MS0031-E-00
-9-
2000/05
AKM [ ASAHI KASEI MICROSYSTEMS ]
