ASAHI KASEI
[AK4556]
SWITCHING CHARACTERISTICS (Continued)
(Ta=-40 ∼ +85°C; VA, VD=2.4 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master mode (VA, VD = 2.4V ∼ 2.7V)
BCLK Frequency
fBCK
dBCK
tMBLR
tBSD
-
64fs
-
-
Hz
%
BCLK Duty
-
50
-
BCLK “↓” to LRCK
BCLK “↓” to SDTO
SDTI Hold Time
−20
−20
20
20
40
40
-
ns
ns
ns
ns
-
tSDH
tSDS
-
SDTI Setup Time
-
-
Master mode (VA, VD = 2.7V ∼ 3.6V)
BCLK Frequency
fBCK
dBCK
tMBLR
tBSD
-
64fs
-
-
Hz
%
BCLK Duty
-
50
-
BCLK “↓” to LRCK
BCLK “↓” to SDTO
SDTI Hold Time
−20
−20
13
13
20
20
-
ns
ns
ns
ns
-
tSDH
tSDS
-
SDTI Setup Time
-
-
Reset Timing
tPW
PDN Pulse Width
PDN “↑” to SDTO valid
Slave Mode
(Note 15)
(Note 16)
150
-
-
ns
Noraml Speed
Double Speed
Quad Speed
tPWV
tPWV
tPWV
tPWV
tPWV
tPWV
-
-
-
-
-
-
4134
8262
-
-
-
-
-
-
1/fs
1/fs
1/fs
1/fs
1/fs
1/fs
16518
4131
Master Mode
Normal Speed
Double Speed
Quad Speed
8259
16515
Note 15. The AK4556 can be reset by bringing the PDN pin = “L”.
Note 16. This cycle is the number of LRCK rising edges from the PDN pin = “H”.
Timing Diagram
1/fCLK
VIH
VIL
MCLK
tCLKH
tCLKL
1/fs
VIH
VIL
LRCK
BCLK
tBCK
VIH
VIL
tBCKH
tBCKL
Figure 2. Clock Timing
MS0559-E-00
2006/11
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
