ASAHI KASEI
[AK4556]
SWITCHING CHARACTERISTICS
(Ta=-40 ∼ +85°C; VA, VD=2.4 ∼ 3.6V; CL=20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing (MCLK)
Frequency: 128fs, 256fs, 512fs
192fs, 384fs, 768fs
fCLK
fCLK
2.048
3.072
-
-
-
-
27.648
MHz
MHz
ns
36.864
Pulse Width Low
tCLKL
tCLKH
0.4/fCLK
0.4/fCLK
-
-
Pulse Width High
ns
LRCK (VA, VD = 2.4V∼3.6V)
Normal Speed: 256fs, 512fs
384fs, 768fs
fs
fs
fs
fs
8
8
-
-
54
48
108
96
55
-
kHz
kHz
kHz
kHz
%
Frequency
Double Speed: 256fs
384fs
54
48
45
-
-
-
Duty Cycle Slave mode
Master mode
-
50
%
LRCK (VA, VD = 2.7V∼3.6V)
Frequency
Quad Speed: 128fs
192fs
fs
fs
108
96
45
-
-
-
216
192
55
-
kHz
kHz
%
Duty Cycle Slave mode
Master mode
-
50
%
Audio Interface Timing
Slave mode (VA, VD = 2.4V ∼ 2.7V)
BCLK Period: Normal Speed
Double Speed
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tDLR
tBSD
tSDH
tSDS
1/128fs
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/64fs
60
60
20
20
-
BCLK Pulse Width Low
Pulse Width High
-
-
LRCK Edge to BCLK “↑”
BCLK “↑” to LRCK Edge
(Note 14)
(Note 14)
-
-
LRCK to SDTO (MSB) (Except I2S mode)
BCLK “↓” to SDTO
40
40
-
-
SDTI Hold Time
20
20
SDTI Setup Time
-
Slave mode (VA, VD = 2.7V ∼ 3.6V)
BCLK Period: Normal Speed
Double / Quad Speed
tBCK
tBCK
tBCKL
tBCKH
tLRB
tBLR
tDLR
tBSD
tSDH
tSDS
1/128fs
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/64fs
33
33
20
20
-
BCLK Pulse Width Low
Pulse Width High
-
-
LRCK Edge to BCLK “↑”
BCLK “↑” to LRCK Edge
(Note 14)
(Note 14)
-
-
LRCK to SDTO (MSB) (Except I2S mode)
BCLK “↓” to SDTO
20
20
-
-
SDTI Hold Time
13
13
SDTI Setup Time
-
Note 14. BCLK rising edge must not occur at the same time as LRCK edge.
MS0559-E-00
2006/11
- 11 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
