ASAHI KASEI
[AK4551]
n Layout Pattern Example
AK4551 requires careful attention to power supply and grounding arrangements to optimize performance.
(Please refer to AKD4551 Evaluation Board layout pattern.)
1. VDD pin should be supplied from analog power supply on system, and VSS pin should be connected to analog
ground on system. The AK4551 is placed on the analog ground plane, and near the analog ground and digital ground
split. And analog and digital ground planes should be only connected at one point. The connection point should be
near to the AK4551.
2. VDD pin should be distributed from the point with low impedance of regulator etc.
3. The series resistors are prevent on the clock lines to reduce overshoot and undershoot. To avoid digital noise
coupling to analog circuit in the AK4551, a 10pF ceramic capacitor on MCLK pin is connected with digital ground.
4. 0.1uF ceramic capacitors of VDD-VSS pins and VCOM-VSS pins should be located as close to the AK4551 as
possible. And these lines should be the shortest connection to pins.
+
4.7u
0.1u
470
2.2n
470
+
+
Rch In
Lch In
AOUTR
AOUTL
VCOM
AINR
AINL
1
2
3
4
5
6
7
8
16
15
2.2n
PWDA 14
PWAD 13
AK4551
Analog Supply
2.2 3.6V
Reset &Power-down
Controller
VSS
51
+
Top View
VDD
SCLK
MCLK
LRCK
SDTI
12
11
10
9
10u 0.1u
51
10P
51
DEM0
DEM1
SDTO
Analog Ground
Digital Ground
51
51
Mode Control
Figure 4. Layout Pattern Example
MS0029-E-00
2000/5
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AKM [ ASAHI KASEI MICROSYSTEMS ]
