ASAHI KASEI
[AK4551]
OPERATION OVERVIEW
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System Clock Input
The AK4551 can be input MCLK=256fs, 384fs or 512fs. The input clock applied to the MCLK as internal master clock is
divided into 256fs automatically. The relationship between the external clock applied to the MCLK input and the desired
sample rate is defined in
Table 1
. The LRCK clock input must be synchronized with MCLK, however the phase is not
critical. *fs is sampling frequency.
When the synchronization is out of phase by changing the clock frequencies during normal operation, the AK4551 may
occur click noise. In case of DAC, click noise is avoided by setting the inputs to “0”.
All external clocks (MCLK, SCLK, LRCK) must be present unless PWAD and PWDA = “L”. If these clocks are not
provided, the AK4551 may draw excess current and may not possibly operate properly because the device utilizes dynamic
refreshed logic internally.
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
MCLK
384fs
12.2880MHz
16.9344MHz
18.4320MHz
SCLK
512fs
16.3840MHz
22.5792MHz
24.5760MHz
32fs
1.0240MHz
1.4112MHz
1.5360MHz
64fs
2.048MHz
2.822MHz
3.072MHz
Table 1. System Clock Example
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Audio Serial Interface Format
Data is shifted in/out the SDTI/SDTO pins using SCLK and LRCK inputs. The data is MSB first, 2’s compliment.
LRCK
SCLK(i)
(64fs)
SDTO(o)
SDTI(i)
0
1
2
12
13
14
20
21
31
0
1
2
12
13
14
20
21
31
0
1
19 18
8
7
6
0
19 18
8
7
6
0
19
Don’t care
19:MSB, 0:LSB
19 18
12 11
1
0
Don’t care
19 18
12 11
1
0
Lch Data
Figure 1. Audio Interface Timing
Rch Data
MS0029-E-00
-8-
2000/5
AKM [ ASAHI KASEI MICROSYSTEMS ]
