[ASAHI KASEI]
Pin/Function
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Signal Name
DVdd1
XTL_IN
(MCLKI)
XTL_OUT(open)
DVss1
SDATA_OUT
BIT_CLK
DVss2
SDATA_IN
DVdd2
SYNC
RESET#
PC_BEEP
PHONE
AUX_L
AUX_R
VIDEO_L
VIDEO_R
CD_L
CD_GND
CD_R
MIC1
MIC2
LINE_IN_L
LINE_IN_R
AVdd1
AVss1
Vref
VrefOut
AFILTL
AFILTR
VRAD
PLLfilter
VRDA
3Dcap
LINE_OUT_L
LINE_OUT_R
MONO_OUT
AVdd2
LNLVL_OUT_L
NC
LNLVL_OUT_R
AVss2
TEST2
TEST3
NC
NC
EAPD
SPDIF_OUT
I/O
-
I
O
-
I
O
-
O
-
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
-
-
O
O
O
O
O
O
O
O
O
O
O
-
O
-
O
-
I
I
-
-
O
O
[AK4545]
Description
Digital power supply; 3.3V(DVdd1 = DVdd2)
0.1uF + 4.7uF capacitors should be connected to digital ground.
24.576MHz(512fs) Crystal is normally connected.
If crystal is not connected, external clock can be used.
24.576MHz(512fs) Crystal. If external clock is used, this pin should be open.
Digital Ground; 0V. This pin should be directly connected to DVss2 on board.
Serial 256-bit AC97 data stream from digital controller
12.288MHz(256fs) serial data clock
Digital Ground; 0V. This pin should be directly connected to DVss1 on board.
Serial 256-bit AC97 data stream to digital controller
Digital power supply; 3.3V(DVdd1 = DVdd2)
0.1uF + 4.7uF capacitors should be connected to digital ground.
AC97 Sync Clock, 48kHz(1fs) fixed rate sampling rate
AC97 Master Hardware Reset
PC Speaker beep pass through
From telephony subsystem speakerphone
Aux Left Channel
Aux Right Channel
Video Audio Left Channel
Video Audio Right Channel
CD Audio Left Channel
CD Audio analog ground
CD_GND or analog ground should be connected through capacitor.
CD Audio Right Channel
Desktop Microphone Input
Second Microphone Input
Line In Left Channel
Line In Right Channel
Power supply; 5.0V(AVdd1=AVdd2)
0.1uF + 4.7uF capacitors should be connected to AVss1(analog ground).
Analog Ground; 0V
Reference Voltage Output;
0.1µF +4.7µF capacitors should be connected to Avss1(analog ground).
Reference Voltage Output (2.5V,1.25mA)
Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor.
Anti-Aliasing Filter Cap; Connected to analog ground with 1nF capacitor.
Vref for ADC ; 0.1uF + 4.7uF capacitors should be connected to analog ground.
Loop filter for PLL is connected ; 36k resistor and 33nF capacitor in series and
390pF capacitor.
Vref for DAC; 0.1uF + 4.7uF capacitors should be connected to analog ground.
3D Enhancement Cap; 27nF capacitor should be connected to analog ground.
Line Out Left Channel
Line Out Right Channel
To telephony subsystem speakerphone
Power supply; 5.0V(AVdd1=AVdd2)
0.1uF capacitor should be connected to AVss2(analog ground).
True Line Level Out Left Channel
No Connection
True Line Level Out Right Channel
Analog Ground
Test pin (This pin should be open for normal operation) :With internal pull-down.
Test pin (This pin should be open for normal operation) :With internal pull-down.
No Connection
No Connection
EAPD(External amplified powerdown)
SPDIF serial data output
MS0058-E-00
-3-
2000/11
AKM [ ASAHI KASEI MICROSYSTEMS ]
