AK4543VQ 参数 Datasheet PDF下载

[ASAHI KASEI]

[AK4543]

Please refer to Powerdown/Powerup sequence of multiple codec configuration on the warm reset when the AK4543

is used under the multiple codec configuration .(See page 24, 25)

nBIT_CLK

Timing

T

clk_high

BIT_CLK

T

clk_low

50%

nSYNC

Timing

T

sync_high

SYNC

T

sync_low

V

IH

V

IL

T

sync_period

nSetup

and Hold Timing

T

delay

BIT_CLK

T

setup

V

OH

V

OL

SDATA_IN

T

hold

SDATA_OUT

SYNC

V

IH

V

IL

V

IH

V

IL

nSignal

Rise and Fall Times

(50pF external load : from 10% 90% of DVdd)

T

rise_clk

BIT_CLK

T

fall_clk

T

rise_din

SDATA_IN

T

fall_din

T

rise_sync

SYNC

T

fall_sync

T

rise_dout

SDATA_OUT

T

fall_dout

nAC-link

Low Power Mode Timing

Slot 1

Slot 2

T

s2_pdwn

BIT_CLK

SDATA_OUT

SDATA_IN

Write to 0x26

Data PR4=1

Don’t care

T

hold

<M0046-E-01>

-9-

1999/01