[ASAHI KASEI]
[AK4543]
When codec ID configuration bits1 and 0 which are set by the codec ID configuration 45/46 strapping pins(codec
ID0# and ID1#) are set to zero(00), the frame is aimed for the Primary codec. And when codec ID configuration bit1
and 0 are set to non-zero values(01, 10, or 11), the frame is meant for Secondary codec.
A new audio output frame begins with a low to high transition of SYNC. SYNC is synchronous to the rising edge of BIT_CLK. On the
immediately following falling edge of BIT_CLK, the AK4543 samples the assertion of SYNC. This falling edge marks the time when
both sides of AC-link are aware of the start of a new audio frame. On the next rising of BIT_CLK, the AC ’97 controller transitions
SDATA_OUT into the first bit position of slot 0 (Valid Frame bit). Each new bit position is presented to AC-link on a rising edge of
BIT_CLK, and subsequently sampled by the AK4543 on the following falling edge of BIT_CLK. This sequence ensures that data
transitions, and subsequent sample points for both incoming and outgoing data streams are time aligned.
Data should be sent to the AC97 codec with MSB first through the Pin labled SDATA_OUT.
The following table shows the relationship of bits14&13 and the Read/Write operations depending on codec ID
configuration.
Bit 15
Valid Frame
Bit 14: Slot1 Valid Bit
(Command Address)
Bit 13: Slot 2 Valid Bit
(Command Data)
Read/Write Operation of
Primary AK4543
Read/Write(Normal Operation)
Ignore
Read: Normal Operation
Write: Ignore
Read/Wirte Operation of
Secondary AK4543
Ignore
Ignore
Ignore
1
1
1
1
0
1
1
1
0
1
0
0
Ignore
Read/Write(Normal Operation)
AK4543 Addressing: Slot0 Tag Bits
b)Slot1:Command Address Port
Slot1 gives the address of the command data, which is given in the slot 2. The AK4543 has 20 valid registers of
16bit data. See Page17(See AC97 register map).
BIT_CLK
Bit19 Bit18 Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit9
Bit2
0
Bit1 Bit0
0 0
Bit19 Bit18 Bit17 Bit16
SDATA_OUT
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 0
Slot 1
0
0 0
Slot 0
Slot 2
Command Address Port
Bit 19:
Bit 18:12
Bit 11:0
Read/Write command
Control Register Index (see AC97 register map for the detail)
Reserved (0)
1=read, 0=write
Bit18 is equivalent to the most significant bit of the index register address.
The AK4543 ignores from bit11 to bit0. These bits will be reserved for future enhancement and must be stuffed
with 0s by the AC97 controller.
c)Slot2:Command Data Port
BIT_CLK
Bit19 Bit18 Bit17 Bit16 Bit15 Bit14 Bit13 Bit12 Bit6
1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
Bit5
Bit4 Bit3
Bit2
0
Bit1 Bit0
0 0
Bit19 Bit18 Bit17 Bit16
SDATA_OUT
1/0 1/0 0
Slot 1
Slot 2
Slot 3
Command Data Port
Bit19:4
Bit3:0
Control Register Write Data (if bit 19 of slot 1 is 1, all Bit19:4 should be 0)
Reserved(0)
If bit19 in slot1 is 0, a write command, the AC97 controller must output Command Data Port data in slot 2 of the
same frame. If the bit19 in slot1 is 1, a read, the AK4543 will ignore any Command Data Port data in slot2.
Bit19 is equivalent to D15 bit of mixer register value.
- 13 -
<M0046-E-01>
1999/01
AKM [ ASAHI KASEI MICROSYSTEMS ]
