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AK4533 参数 Datasheet PDF下载

AK4533图片预览
型号: AK4533
PDF下载: 下载PDF文件 查看货源
内容描述: 音频编解码器,触摸屏控制器 [Audio Codec with Touch Screen Controller]
分类和应用: 解码器编解码器控制器
文件页数/大小: 40 页 / 456 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[ASAHI KASEI]  
Table 2 shows the control registers. (See " „Touch Screen Control Register " for the detail of 07h register)  
Note that MCLK should be present when a register is accessed.  
D7  
AGC  
LSTEP1  
X
D6  
X
D5  
X
D4  
X
D3  
X
D2  
X
D1  
TH1  
D0  
Addr  
00  
01  
02  
03  
Default  
03  
01  
10  
36  
TH0  
AGC Control  
Limit/Recovery Control  
IPGA Control  
Recovery Reference Level  
DATT Control  
Audio Powerdown &  
Clock Control  
LSTEP0  
IPGA6  
REF6  
X
X
X
RSTEP1 RSTEP0  
RWT1  
IPGA1  
REF1  
M1  
RWT0  
IPGA0  
REF0  
M0  
IPGA5  
REF5  
X
IPGA4  
REF4  
X
IPGA3  
REF3  
M3  
IPGA2  
REF2  
M2  
X
Mute  
MSEL  
04  
05  
00  
07  
X
X
X
X
DARPD  
DALPD  
ADPD  
X
X
X
X
X
X
X
X
X
X
06  
07  
Reserve  
Touch Screen Control  
00  
80  
TSPD  
PW  
D3  
D2  
D1  
D0  
(The value of the registers is cleared and is set to default value when PDB pin or RESETB is set to "L".)  
Table 2. The AK4533 Register Map  
AGC Control  
When AGC bit is set to "0", AGC operation is inhibited. IPGA can be changed by writing to IPGA Control Register directly if AGC bit  
is "0". When AGC bit is set to "1", AGC function is activated.  
Before AGC operation, related registers, 00h - 03h, and MSEL (05h), should be set to appropriate value. (TH1/TH0 bits and AGC bit  
can be set at the same time.)  
Note that MSEL bit must be changed under power-down state (D0, D1, and D2 is set to "1")  
When AGC operation starts, the AK4533 uses the value of IPGA Control Register as initial value. After that, IPGA value is updated  
automatically. When the read of 02h register is executed, the AK4533 outputs the value which is updated by AGC circuit. Note that the  
value is not the same as the value that was stored at the start of AGC operation. The write operation to 02h register is ignored.  
When ADC is set to power-down mode (ADPD="1"), 00h - 03h registers are set to default values. After power-down mode is cleared  
(ADPD = "0"), the write to the register is enabled. The period (516Ts@ MSEL="1", 260TS@MSEL=“0”) is required until VREFAD  
is stable. The write to the registers is possible in this initial period, but AGC function is disabled for this period. The AK4533 initiates  
AGC operation automatically after the end of the period.  
Addr = 00h  
AGC:  
AGC Operation Enable  
(0: Disable  
1: Enable)  
“1”: AGC Operation ”0”: Gain can be changed directly through A/T I/F  
<Revision 0.9a>  
19  
July 00  
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