[ASAHI KASEI]
(b) Audio/Touch Screen Control Interface(A/T I/F)
The AK4533 incorporates 4 pin (CCLK, CS, CDTO, and CDTI) digital serial interface that links it to the external controller. This
interface is used to access to the internal register. T/C I/F protocol has 16 bit field, and consists of three groups; one write/read bit, three
address bits, and eight control bits. Data format is MSB first.
Write to the register
A/T interface is enabled by the CS pin = "H". In this mode, internal registers may be either written to or read from 4-wire uP interface.
The device can recognizes the write request by the first bit = "1". Address and data is also clocked in via CDTI pin at the rising edge of
CCLK. For write operation the control data is latched at the rising edge of 16th CCLK, after high-to-low transition. When more than
16 CCLK is input, the device ignores the CCLK. CS can be returned to "L" at the same time of 16th falling edge of CCLK. CS pin
should be "L" once after the write cycle terminates.
For read operation, the device can recognizes the read request by the first bit = "0". Address is clocked in via CDTI pin at the rising
edge of CCLK. The AK4533 outputs the addressed value via CDTO pin from the 8th falling edge of CCLK. At the 16th falling edge
of CCLK, CDTO outputs "L". When more than 16 CCLK is input, CDTO still outputs "L". CS can be returned to "L" at the same time
of 16th falling edge of CCLK. CS pin should be "L" once after the write cycle terminates.
CCLK, CS, and CDTI should be "L" while the device is idle state. CDTO is "L" under idle state.
("Idle state" means that the read/write operation is NOT executed)
1
8
9
16
CCLK(i)
CS(i)
“L”
“L”
“1” A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
CDTI(i)
“L”
“L”
(1) Write to the register
1
8
9
16
“L”
“L”
CCLK(i)
CS(i)
“0” A2 A1 A0
CDTI(i)
“L”
“L”
“L”
“L”
D7 D6 D5 D4 D3 D2 D1 D0
CDTO(o)
(2)Read from the register
Address D7-D0:
A2-A0:
Data
Figure 12. Audio/Touch Screen Control Interface Timing
<Revision 0.9a>
18
July 00
AKM [ ASAHI KASEI MICROSYSTEMS ]
