ASAHI KASEI
[AK4528]
In case of parallel mode, both ADC and DAC are powered up with releasing internal reset state when PDN is set to “H”.
Therefore each outputs start to output at once. However the initialization of ADC/DAC, and the fade-in cycle of OATT
(8031/fs) are exist.
Power Supply
PDN pin
ADC Internal State
PD
INITA
Normal
PD
INITA
INITD
Normal
SDTO
“0”
INITD
00H
Output
Normal
“0”
Output
Normal
DAC Internal State
OATT
PD
PD
00H
7FH
7FH
00H
00H
*
7FH
®
7FH
Output
®
512/fs
512/fs
AOUT
Hi-Z
FI
Output
Hi-Z
FI
*
*
External Mute
Example
External clocks
MCLK, LRCK, BICK
The clocks can be stopped.
MCLK, LRCK, BICK
· INITA:
· INITD:
· PD:
Initializing period of ADC analog section (516/fs).
Initializing period of DAC analog section (512/fs).
Power down state.
· FI:
· AOUT:
Fade in. After exiting power down state, ATT value fades in by 8032/fs cycles.
Some pop noise may occur at “*”.
Figure 8. Reset & Power Down Sequence in Parallel Mode
MS0011-E-00
2000/1
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AKM [ ASAHI KASEI MICROSYSTEMS ]
