ASAHI KASEI
[AK4528]
n Audio Serial Interface Format
In case of serial mode, the DIF0-2 bits as shown in Table 4 support five serial formats. In case of parallel mode, two
formats (Mode 2 and 3) are supported by DIF pin (Table 5). In all modes the serial data is MSB-first, 2’s compliment
format. The SDTO is clocked out on the falling edge of BICK and the SDTI is latched on the rising edge.
Mode DIF2 bit DIF1 bit DIF0 bit
SDTO
SDTI
LRCK
H/L
BICK
³ 32fs
³ 40fs
³ 48fs
³ 48fs
³ 48fs
0
1
2
3
4
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
24bit, MSB justified
24bit, MSB justified
24bit, MSB justified
24bit, I2S
16bit, LSB justified
20bit, LSB justified
24bit, MSB justified
24bit, I2S
H/L
Default
H/L
L/H
24bit, MSB justified
24bit, LSB justified
H/L
Table 4. Audio data format in Serial Mode
Mode
DIF pin
SDTO
SDTI
LRCK
H/L
BICK
³ 48fs
³ 48fs
2
3
0
1
24bit, MSB justified
24bit, I2S
24bit, MSB justified
24bit, I2S
L/H
Table 5. Audio data format in Parallel Mode
LRCK
0
1
2
3
9
10
11
12
13
14
15
0
1
2
9
10
11
12
13 14
15
0
1
BICK(32fs)
SDTO(o)
23 22 21
15 14 13
15 14 13 12 11 10
9
1
8
0
23 22 21
15 14 13
15 14 13 12 11 10
9
1
8
0
23
15
7
6
5
4
3
2
7
6
5
4
3
2
SDTI(i)
0
1
2
3
17
18
19 20
30
31
0
1
2
3
17
18 19
20
31
0
1
BICK(64fs)
SDTO(o)
23 22 21
7
6
5
4
3
23 22 21
7
6
5
4
3
23
15 14 13 12 11
2
1
0
15 14 13 12 11
Rch Data
2
1
0
Don’t Care
Don’t Care
SDTI(i)
SDTO-19:MSB, 0:LSB; SDTI-15:MSB, 0:LSB
Lch Data
Figure 1. Mode 0 Timing
LRCK
0
1
2
12
13
14
24
25
31
0
1
2
12
13
14
24
25
31
0
1
BICK(64fs)
SDTO(o)
23 22
12 11 10
19 18
0
8
23 22
12 11 10
19 18
Don’t Care
0
8
23
7
1
0
7
1
0
Don’t Care
SDTI(i)
SDTO-23:MSB, 0:LSB; SDTI-19:MSB, 0:LSB
Lch Data
Rch Data
Figure 2. Mode 1 Timing
MS0011-E-00
2000/1
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AKM [ ASAHI KASEI MICROSYSTEMS ]
