ASAHI KASEI
[AK4528]
OPERATION OVERVIEW
n System Clock Input
The external clocks, which are required to AK4528, are MCLK, BICK and LRCK. MCLK should be synchronized with
LRCK but the phase is not critical. The frequency of MCLK is set by CMODE, CKS0-1 and DFS bits in serial mode, or by
CKS0-1, DFS pins in parallel mode (see Table 2 and 3). The CKS0-1 and DFS pin should be changed during the PDN pin
= “L”. The CMODE, CKS0-1 and DFS bits are changed during RSTADN=RSTDAN= “0”.
External clocks (MCLK, BICK and LRCK) should always be present whenever the AK4528 is in normal operation mode
(PDN=”H” and at least one of ADC and DAC is in normal operation mode). If these clocks are not provided, the AK4528
may draw excess current because the device utilizes dynamic refreshed logic internally. If the external clocks are not
present, the AK4528 should be in the power-down mode (PDN=”L” or set both ADC and DAC power down mode by the
register).
MCLK
MCLK
CMODE bit CKS1 bit CKS0 bit
Normal Speed
(DFS bit=”0”)
Double Speed
(DFS bit=”1”)
Default
0
0
0
1
1
0
0
1
0
0
0
1
0
0
1
256fs
512fs
1024fs
384fs
768fs
N/A
256fs
512fs
N/A
384fs
Table 1. Master Clock Frequency Select in Serial Mode
MCLK
MCLK
CKS1 pin CKS0 pin
Normal Speed
(DFS pin = “L”)
Double Speed
(DFS pin = “H”)
L
L
L
H
L
256fs
512fs
384fs
1024fs
N/A
256fs
N/A
H
H
H
512fs
Table 2. Master Clock Frequency Select in Parallel Mode
MCLK
MCLK
fs=44.1kHz
fs=48kHz
fs=88.2kHz
fs=96kHz
Normal Speed
Double Speed
(DFS = “0”)
256fs
(DFS = “1”)
N/A
11.2896MHz 12.288MHz
22.5792MHz 24.576MHz
45.1584MHz 49.152MHz
16.9344MHz 18.432MHz
33.8688MHz 36.864MHz
N/A
N/A
512fs
1024fs
384fs
256fs
512fs
N/A
384fs
22.5792MHz
45.1584MHz
N/A
24.576MHz
49.152MHz
N/A
768fs
33.8688MHz
36.864MHz
Table 3. Master Clock Frequencies example
Note. Do not set any mode which is not described in Table1-3.
MS0011-E-00
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AKM [ ASAHI KASEI MICROSYSTEMS ]
