[AK4497]
(Ta=25C; AVDD=TVDD=3.3V, DVDD=1.8V(@LDOE pin= “L”), AVSS=DVSS=VSSL/R=0V;
VREFHL/R=VDDL/R=5.0V, VREFLL/R= 0V; Input data = 24bit; BICK=64fs; Signal Frequency = 1kHz;
Sampling Frequency = 44.1kHz; SC[2:0] bits= “000”); 2Vrms output mode (GC[2:0] bits= “000” or GAIN
pin = “L”); Heavy load drive mode=off (HLOAD bit= “0” or HLOAD pin= “L”); unless otherwise specified.)
Power Supplies
Parameter
Min.
Typ.
Max.
Unit
Power Supply Current
Normal operation (PDN pin = “H”)
VDDL/R(total)
VREFHL/R
64
1
1
96
1.5
1.5
mA
mA
mA
AVDD
-
TVDD
fs= 44.1kHz
fs= 96kHz
fs = 192kHz
8
13
20
1
12
20
30
1.5
mA
mA
mA
mA
LDOE pin = “H”
-
-
LDOE pin = “L”
DVDD
fs= 44.1kHz
fs= 96kHz
fs = 192kHz
8
13
20
12
20
30
mA
mA
mA
LDOE pin = “L”
Total Idd per channel (HLOAD pin = “H”)
・fs=44.1kHz
45
72
mA/ch
Power down (PDN pin = “L”)
(Note 18)
TVDD+AVDD+VDDL/R+DVDD
-
10
100
A
Note 18. In power down mode, the PSN pin = TVDD and all other digital input pins including clock pins
(MCLK, BICK and LRCK) are held to DVSS.
Note 19. The DVDD pin becomes an output pin when the LDOE pin = “H”.
016003187-E-00
2016/05
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
