[AK4421]
OPERATION OVERVIEW
■
System Clock
The external clocks required to operate the AK4421 are MCLK, LRCK, and BICK. The master clock (MCLK) should be
synchronized with LRCK, but the phase is not critical. The MCLK is used to operate the digital interpolation filter and the
delta-sigma modulator. Sampling speed and MCLK frequency are detected automatically, and then the internal master
clock is set to the appropriate frequency (Table
1).
The AK4421 is automatically placed in power saving mode when MCLK and LRCK stop during normal operation mode,
and the analog output goes to 0V(typ). When MCLK and LRCK are input again, the AK4421 is powered up. After exiting
reset following power-up, the AK4421 is not fully operational until MCLK and LRCK are input.
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
MCLK (MHz)
256fs
384fs
512fs
-
-
16.3840
-
-
22.5792
-
-
24.5760
22.5792
33.8688
-
24.5760
36.8640
-
-
-
-
-
-
-
Table 1. System Clock Example
When MCLK= 256fs/384fs, the Auto Setting Mode supports sampling rate of 32kHz~96kHz (Table
1).
But, when the
sampling rate is 32kHz~48kHz, DR and S/N will degrade by approximately 3dB as compared to when MCLK=
512fs/768fs (Table
2).
MCLK
DR,S/N
256fs/384fs
99dB
512fs/768fs
102dB
Table 2. Relationship between MCLK frequency and DR, S/N (fs= 44.1kHz)
Sampling
Speed
Normal
Double
Quad
128fs
-
-
-
-
-
22.5792
24.5760
192fs
-
-
-
-
-
33.8688
36.8640
768fs
24.5760
33.8688
36.8640
-
-
-
-
1152fs
36.8640
-
-
-
-
-
-
■
Audio Serial Interface Format
The audio data is shifted in via the SDTI pin using the BICK and LRCK inputs. The DIF pin can select between two serial
data modes as shown in
In all modes the serial data is MSB-first, two’s complement format and it is latched on
the rising edge of BICK. In one cycle of LRCK, eight “H” pulses or more must not be input to the DIF pin.
Mode
0
1
DIF
L
H
SDTI Format
24bit MSB justified
24bit I
2
S
BICK
≥48fs
≥48fs
Figure
Table 3. Audio Data Formats
MS0945-E-01
-9-
2008/08
AKM [ ASAHI KASEI MICROSYSTEMS ]
