[AK4414]
スイッチング特性
(Ta=25°C; VDD1/2=4.75 ∼ 5.25V, AVDD=DVDD=2.7 ∼ 3.6V)
Parameter
Symbol
min
typ
max
Unit
Master Clock Timing
Frequency
fCLK
dCLK
2.048
40
41.472
60
MHz
%
Duty Cycle
LRCK Frequency (Note 16)
Normal Mode (TDM0= “L”, TDM1= “L”)
1152fs, 512fs or 768fs
256fs or 384fs
128fs or 192fs
Duty Cycle
fsn
fsd
8
54
108
216
55
kHz
kHz
kHz
%
54
fsq
108
45
Duty
TDM256 mode (TDM0= “H”, TDM1= “L”)
Normal Speed Mode High time
Low time
fsn
tLRH
tLRL
8
54
kHz
ns
ns
1/256fs
1/256fs
TDM128 mode (TDM0= “H”, TDM1= “H”)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
High time
Low time
fsn
fsd
8
54
108
1/128fs
1/128fs
54
108
216
kHz
kHz
kHz
ns
fsq
tLRH
tLRL
ns
PCM Audio Interface Timing
Normal Mode (TDM0= “L”, TDM1= “L”)
BICK Period
1152fs, 512fs or 768fs
256fs or 384fs
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
1/128fsn
ns
ns
ns
ns
ns
ns
ns
ns
ns
1/64fsd
128fs or 192fs
1/64fsq
BICK Pulse Width Low
BICK Pulse Width High
14
14
14
14
5
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDATA Hold Time
(Note 17)
(Note 17)
tLRB
tSDH
tSDS
SDATA Setup Time
5
TDM256 mode (TDM0= “H”, TDM1= “L”)
BICK Period
Normal Speed Mode
BICK Pulse Width Low
BICK Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDATA1/2 Hold Time
SDATA1/2 Setup Time
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
1/256fsn
ns
ns
ns
ns
ns
ns
ns
14
14
14
14
5
(Note 17)
(Note 17)
5
MS1476-J-00
2013/01
- 14 -