ASAHI KASEI
[AK4393]
OPERATION OVERVIEW
n System Clock
The external clocks, which are required to operate the AK4393, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. The sampling speed is set by DFS (Table 1). The sampling rate (LRCK), CKS0/1/2
and DFS determine the frequency of MCLK (Table 2).
All external clocks (MCLK, BICK and LRCK) should always be present whenever the AK4393 is in normal operation
mode (PDN = “H”). If these clocks are not provided, the AK4393 may draw excess current because the device utilizes
dynamic refreshed logic internally. If the external clocks are not present, the AK4393 should be in the power-down mode
(PDN = “L”) or in the reset mode (RSTN = “0”). After exiting reset at power-up etc., the AK4393 is in power-down mode
until MCLK and LRCK are input.
DFS
Sampling Rate (fs)
Default
0
1
Normal Speed Mode
Double Speed Mode
30kHz~54kHz
60kHz~108kHz
Table 1. Sampling Speed
Double
Mode
CKS2
CKS1
CKS0
Normal
Default
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
256fs
256fs
384fs
384fs
512fs
512fs
768fs
768fs
128fs
256fs
192fs
384fs
256fs
N/A
384fs
N/A
Table 2. System Clocks
LRCK
fs
MCLK
BICK
64fs
256fs
384fs
512fs
768fs
32.0kHz
8.1920MHz 12.2880MHz 16.3840MHz 24.5760MHz 2.0480MHz
44.1kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 2.8224MHz
48.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 3.0720MHz
Table 3. System clock example (Normal Speed Mode)
LRCK
fs
MCLK
BICK
64fs
128fs
192fs
256fs
384fs
88.2kHz 11.2896MHz 16.9344MHz 22.5792MHz 33.8688MHz 5.6448MHz
96.0kHz 12.2880MHz 18.4320MHz 24.5760MHz 36.8640MHz 6.1440MHz
Table 4. System clock example (Double Speed Mode)
M0039-E-01
2000/5
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AKM [ ASAHI KASEI MICROSYSTEMS ]
