[AK4388A]
■ System Reset
The AK4388A must be reset once by bringing the RSTN pin = “L” upon power-up. The AK4388A is powered up and the
internal timing starts clocking by LRCK “↑” after exiting reset by MCLK. The AK4388A is in reset state until LRCK is
input.
■ Power ON/OFF timing
The AK4388A is placed in the power-down mode by bringing the RSTN pin “L” and the registers are initialized. The
analog outputs go to VCOM (VDD/2). Since click noise occurs at the edge of the RSTN signal, the analog output should
be muted externally if click noise aversely affects system application.
Power
RSTN pin
Internal
State
(2)
Normal Operation
Reset
DAC In
(Digital)
(2)
“0”data
“0”data
GD
(1)
GD
(3)
(3)
DAC Out
(Analog)
(5)
DZF
External
Mute
(4)
Mute ON
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are VCOM (VDD/2) in power-down mode.
(3) Click noise occurs at the edge of RSTN signal. This noise is output even if “0” data is input.
(4) Mute the analog output externally if the click noise (3) influences the system application.
The timing example is shown in this figure.
(5) DZF pins are “L” in the power-down mode (RSTB pin = “L”).
Figure 9. Power-down/up Sequence Example
MS1008-E-02
2010/09
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
