ASAHI KASEI
[AK4386]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.2
∼
3.6V)
Parameter
Master Clock Frequency
Half Speed Mode (512/768/1024/1536fs)
Normal Speed Mode (256/384/512/768fs)
Double Speed Mode (128/192/256/384fs)
Duty Cycle
LRCK Frequency
Half Speed Mode
(DFS1-0 = “10”)
Normal Speed Mode (DFS1-0 = “00”)
Double Speed Mode (DFS1-0 = “01”)
Duty Cycle
Audio Interface Timing
BICK Period
Half Speed Mode
Normal Speed Mode
Double Speed Mode
BICK Pulse Width Low
Pulse Width High
BICK “↑” to LRCK Edge
LRCK Edge to BICK “↑”
SDTI Hold Time
SDTI Setup Time
Power-Down & Reset Timing
PDN Pulse Width
Symbol
fCLK
fCLK
fCLK
dCLK
fsh
fsn
fsd
dCLK
min
4.096
2.048
6.144
40
8
8
48
45
typ
max
36.864
36.864
36.864
60
24
48
96
55
Units
MHz
MHz
MHz
%
kHz
kHz
kHz
%
(Note 8)
(Note 8)
tBCK
tBCK
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
tPD
1/128fs
1/128fs
1/64fs
70
70
40
40
40
40
4
×
C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
(Note 9)
Note 8. BICK rising edge must not occur at the same time as LRCK edge.
Note 9. The AK4386 can be reset by bringing PDN pin = “L”.
The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4
×
C.
When C = 4.7µF, tPD is 19ms(min).
The value of the capacitor (C) connected with VCOM pin should be 1µF
≤
C
≤
10µF.
When the states of DIF1-0 pins change, the AK4386 should be reset by PDN pin.
MS0280-E-00
-7-
2003/12
AKM [ ASAHI KASEI MICROSYSTEMS ]
