ASAHI KASEI
[AK4384]
Ordering Guide
AK4384ET
AK4384VT
AKD4384
-20
∼
+85°C
16pin TSSOP (0.65mm pitch)
-40
∼
+85°C
16pin TSSOP (0.65mm pitch)
Evaluation Board for AK4384
Pin Layout
MCLK
BICK
SDTI
LRCK
PDN
SMUTE/CSN
ACKS/CCLK
DIF0/CDTI
1
2
3
4
5
6
7
8
16
15
14
DZFL
DZFR
VDD
VSS
VCOM
AOUTL
AOUTR
P/S
Top
View
13
12
11
10
9
PIN/FUNCTION
Function
Master Clock Input Pin
An external TTL clock should be input on this pin.
2
BICK
I
Audio Serial Data Clock Pin
3
SDTI
I
Audio Serial Data Input Pin
4
LRCK
I
L/R Clock Pin
5
PDN
I
Power-Down Mode Pin
When at “L”, the AK4384 is in the power-down mode and is held in reset. The
The AK4384 must be reset once upon power-up.
6
SMUTE
I
Soft Mute Pin in parallel mode
“H”: Enable, “L”: Disable
CSN
I
Chip Select Pin in serial mode
7
ACKS
I
Auto Setting Mode Pin in parallel mode
“L”: Manual Setting Mode, “H”: Auto Setting Mode
CCLK
I
Control Data Clock Pin in serial mode
8
DIF0
I
Audio Data Interface Format Pin in parallel mode
CDTI
I
Control Data Input Pin in serial mode
9
P/S
I
Parallel/Serial Select Pin
(Internal pull-up pin)
“L”: Serial control mode, “H”: Parallel control mode
10
AOUTR
O
Rch Analog Output Pin
11
AOUTL
O
Lch Analog Output Pin
12
VCOM
O
Common Voltage Pin, VDD/2
Normally connected to VSS with a 0.1µF ceramic capacitor in parallel with a
10µF electrolytic cap.
13
VSS
-
Ground Pin
14
VDD
-
Power Supply Pin
15
DZFR
O
Rch Data Zero Input Detect Pin
16
DZFL
O
Lch Data Zero Input Detect Pin
Note: All input pins except pull-up pin should not be left floating.
MS0176-E-01
-2-
2006/01
No.
1
Pin Name
MCLK
I/O
I
AKM [ ASAHI KASEI MICROSYSTEMS ]
