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AK4384ET 参数 Datasheet PDF下载

AK4384ET图片预览
型号: AK4384ET
PDF下载: 下载PDF文件 查看货源
内容描述: 106分贝192kHz的24位双声道ツヒDAC [106dB 192kHz 24-Bit 2ch ツヒ DAC]
分类和应用:
文件页数/大小: 24 页 / 277 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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ASAHI KASEI
[AK4384]
OPERATION OVERVIEW
System Clock
The external clocks, which are required to operate the AK4384, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS =
“0”: Register 00H), the sampling speed is set by DFS0/1(Table 1). The frequency of MCLK at each sampling speed is set
automatically. (Table 2~4).After exiting reset (PDN = “↑”), the AK4384 is in Auto Setting Mode. In Auto Setting Mode
(ACKS = “1”: Default), as MCLK frequency is detected automatically (Table 5), and the internal master clock becomes
the appropriate frequency (Table 6), it is not necessary to set DFS0/1.
In parallel mode, the sampling speed can be set by ACKS pin. The internal DFS0 andDFS1 bits are fixed to “0”.
Therefore, when ACKS pin is “L”, the AK4384 operates in Normal Speed Mode. The AK4384 operates in Auto Setting
Mode at ACKS = “H”. In parallel mode, the AK4384 does not support 128fs and 192fs of Double Speed Mode.
All external clocks (MCLK,BICK and LRCK) should always be present whenever the AK4384 is in the normal operation
mode (PDN= ”H”). If these clocks are not provided, the AK4384 may draw excess current and may fall into unpredictable
operation. This is because the device utilizes dynamic refreshed logic internally. The AK4384 should be reset by PDN=
“L” after threse clocks are provided. If the external clocks are not present, the AK4384 should be in the power-down
mode (PDN= “L”). After exiting reset at power-up etc., the AK4384 is in the power-down mode until MCLK and LRCK
are input.
DFS1
0
0
1
DFS0
0
1
0
Sampling Rate (fs)
Normal Speed Mode
Double Speed Mode
Quad Speed Mode
8kHz~48kHz
60kHz~96kHz
120kHz~192kHz
Default
Table 1. Sampling Speed (Manual Setting Mode)
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
256fs
8.1920MHz
11.2896MHz
12.2880MHz
384fs
12.2880MHz
16.9344MHz
18.4320MHz
MCLK
512fs
16.3840MHz
22.5792MHz
24.5760MHz
768fs
24.5760MHz
33.8688MHz
36.8640MHz
1152fs
36.8640MHz
N/A
N/A
BICK
64fs
2.0480MHz
2.8224MHz
3.0720MHz
Table 2. System Clock Example (Normal Speed Mode @Manual Setting Mode)
LRCK
fs
88.2kHz
96.0kHz
MCLK
128fs
11.2896MHz
12.2880MHz
192fs
16.9344MHz
18.4320MHz
256fs
22.5792MHz
24.5760MHz
384fs
33.8688MHz
36.8640MHz
BICK
64fs
5.6448MHz
6.1440MHz
Table 3. System Clock Example (Double Speed Mode @Manual Setting Mode)
MS0176-E-01
-9-
2006/01