ASAHI KASEI
[AK4367]
DC CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2
∼
3.6V)
Parameter
Symbol
min
High-Level Input Voltage
VIH
70%DVDD
Low-Level Input Voltage
VIL
-
Input Voltage at AC Coupling
(Note 16)
VAC
1.0
Low-Level Output Voltage
(Iout = 3mA)
VOL
-
Input Leakage Current
(Note 17)
Iin
-
Note 16. Only MCLK pin. (Figure 33)
Note 17. I2C pin has internal pull-down device, nominally 100kΩ.
typ
-
-
-
-
-
max
-
30%DVDD
-
0.4
±10
Units
V
V
Vpp
V
µA
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD, HVDD=2.2
∼
3.6V; C
L
= 20pF)
Parameter
Symbol
min
typ
max
Units
Master Clock Timing
Frequency
fCLK
2.048
-
24.576
MHz
Pulse Width Low
(Note 18)
tCLKL
0.4/fCLK
-
-
ns
Pulse Width High
(Note 18)
tCLKH
0.4/fCLK
-
-
ns
AC Pulse Width
(Note 21)
tACW
20
-
-
ns
LRCK Timing
Frequency
fs
8
44.1
48
kHz
Duty Cycle:
Duty
45
-
55
%
Serial Interface Timing
(Note 19)
BICK Period
tBCK
1/(64fs)
-
-
ns
BICK Pulse Width Low
tBCKL
130
-
-
ns
Pulse Width High
tBCKH
130
-
-
ns
(Note 20)
tLRB
50
-
-
ns
LRCK Edge to BICK “↑”
(Note 20)
tBLR
50
-
-
ns
BICK “↑” to LRCK Edge
SDATA Hold Time
tSDH
50
-
-
ns
SDATA Setup Time
tSDS
50
-
-
ns
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
-
-
ns
CCLK Pulse Width Low
tCCKL
80
-
-
ns
Pulse Width High
tCCKH
80
-
-
ns
CDTI Setup Time
tCDS
40
-
-
ns
CDTI Hold Time
tCDH
40
-
-
ns
CSN “H” Time
tCSW
150
-
-
ns
tCSS
50
-
-
ns
CSN “↑” to CCLK “↑”
tCSH
50
-
-
ns
CCLK “↑” to CSN “↑”
Note 18. Except AC coupling.
Note 19. Refer to “Serial Data Interface”.
Note 20. BICK rising edge must not occur at the same time as LRCK edge.
Note 21. Pulse width to ground level when MCLK is connected to a capacitor in series and a resistor is connected to
ground. (Refer to Figure 3.)
MS0247-E-02
-9-
2005/10
AKM [ ASAHI KASEI MICROSYSTEMS ]
