ASAHI KASEI
[AK4367]
OPERATION OVERVIEW
System Clock
The external clocks required to operate the AK4367 are MCLK(256fs/384fs/512fs), LRCK(fs) and BICK. The master
clock (MCLK) should be synchronized with sampling clock (LRCK). The phase between these clocks does not matter.
The frequency of MCLK is detected automatically, and the internal master clock becomes the appropriate frequency.
Table 1 shows system clock example.
LRCK
fs
8kHz
MCLK (MHz)
384fs
BICK (MHz)
64fs
256fs
2.048
512fs
4.096
3.072
0.512
11.025kHz
12kHz
16kHz
22.05kHz
24kHz
32kHz
44.1kHz
48kHz
2.8224
3.072
4.096
5.6448
6.144
8.192
4.2336
4.608
6.144
8.4672
9.216
12.288
16.9344
18.432
5.6448
6.144
8.192
11.2896
12.288
16.384
22.5792
24.576
0.7056
0.768
1.024
1.4112
1.536
2.048
11.2896
12.288
2.8224
3.072
Table 1. System Clock Example
All external clocks (MCLK, BICK and LRCK) should always be present whenever the DAC is in normal operation mode
(PMDAC bit = “1”). If these clocks are not provided, the AK4367 may draw excess current and will not operate properly
because it utilizes these clocks for internal dynamic refresh of registers. If the external clocks are not present, the DAC
should be placed in power-down mode (PMDAC bit = “0”). When MCLK is input with AC coupling, the MCKAC bit
should be set to “1”.
For low sampling rates, DR and S/N degrade because of the outband noise. DR and S/N are improved by setting DFS1 bit
to “1”. Table 2 shows S/N of DAC output for both the HP-amp and MOUT. When the DFS1 bit is “1”, MCLK needs
512fs.
Over Sample
Rate
S/N (fs=8kHz, A-weighted)
DFS1
DFS0
fs
MCLK
HP-amp
MOUT
56dB
75dB
90dB
0
0
1
0
1
x
64fs
128fs
256fs
256fs/384fs/512fs
256fs/384fs/512fs
512fs
56dB
Default
8kHz∼48kHz
8kHz∼24kHz
8kHz∼12kHz
75dB
92dB
Table 2. Relationship among fs, MCLK frequency and S/N of HP-amp and MOUT
MS0247-E-02
2005/10
- 13 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
