[AK4359A]
Master Clock
1
2
3
4
5
6
7
8
9
MCLK
BICK
DZF1 30
DZF2 29
AVDD 28
64fs
0.1u
0.1u
10u
24bit Audio Data
SDTI1
LRCK
RSTB
Analog 5V
+
10u
AVSS
fs
27
+
Reset
VCOM 26
LOUT1 25
ROUT1 24
10u
MUTE
MUTE
CSN
L1ch Out
R1ch Out
10u
AK4359A
Micro-
CCLK
CDTI
SDTI2
controller
P/S
23
24bit Audio Data
24bit Audio Data
24bit Audio Data
Micro-
LOUT2 22
ROUT2 21
MUTE
MUTE
L2ch Out
R2ch Out
10 SDTI3
11 SDTI4
12 TDM0
13 DEM0
LOUT3
20
MUTE
MUTE
L3ch Out
R3ch Out
L4ch Out
R4ch Out
ROUT3 19
LOUT4 18
ROUT4 17
I2C 16
controller
MUTE
MUTE
10u
14
15
DVDD
DVSS
+
0.1u
Digital 5V
Digital Ground
Analog Ground
Figure 24. Typical Connection Diagram (3-wire Serial Control Mode)
Notes:
- LRCK = fs, BICK = 64fs.
- When AOUT drives some capacitive load, some resistor should be added in series between AOUT and
capacitive load.
- All input pins except pull-up pin should not be left floating.
MS1010-E-01
2008/10
- 30 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
