[AK4344]
SWITCHING CHARACTERISTICS
(Ta=25°C; VDD=2.7
∼
3.6V; C
L
= 20pF)
Parameter
Symbol
min
Master Clock Frequency
Half Speed Mode (512/768/1024/1536fs)
fCLK
4.096
Normal Speed Mode (256/384/512/768fs)
fCLK
2.048
Double Speed Mode (128/192/256/384fs)
fCLK
6.144
Duty Cycle
dCLK
40
LRCK Frequency
Half Speed Mode
(DFS1-0 = “10”)
fsh
8
Normal Speed Mode (DFS1-0 = “00”)
fsn
8
Double Speed Mode (DFS1-0 = “01”)
fsd
48
Duty Cycle
dCLK
45
Audio Interface Timing
BICK Period
1/128fs
tBCK
Half Speed Mode
1/128fs
tBCK
Normal Speed Mode
1/64fs
tBCK
Double Speed Mode
70
tBCKL
BICK Pulse Width Low
70
tBCKH
Pulse Width High
40
tBLR
BICK “↑” to LRCK Edge
40
tLRB
LRCK Edge to BICK “↑”
40
tSDH
SDTI Hold Time
40
tSDS
SDTI Setup Time
Control Interface Timing
200
CCLK Period
tCCK
80
CCLK Pulse Width Low
tCCKL
80
Pulse Width High
tCCKH
40
CDTI Setup Time
tCDS
40
CDTI Hold Time
tCDH
150
CSN “H” Time
tCSW
150
CSN “↓” to CCLK “↑”
tCSS
50
tCSH
CCLK “↑” to CSN “↑”
tDCD
CDTO Delay
tCCZ
CSN “↑” to CDTO Hi-Z
Power-Down & Reset Timing
PDN Pulse Width
tPD
4
typ
max
36.864
36.864
36.864
60
24
48
96
55
Units
MHz
MHz
MHz
%
kHz
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms/μF
45
70
Note 11. BICK rising edge must not occur at the same time as LRCK edge.
Note 12. The AK4344 can be reset by bringing PDN pin = “L”.
The PDN pulse width is proportional to the value of the capacitor (C) connected to VCOM pin. tPD = 4000× C.
When C = 4.7μF, tPD is 19ms(min).
The value of the capacitor (C) connected with VCOM pin should be 1μF
≤
C
≤
10μF.
When the states of DIF1-0 pins change, the AK4344 should be reset by PDN pin.
MS0641-E-00
-8-
2007/06
AKM [ ASAHI KASEI MICROSYSTEMS ]
