ASAHI KASEI
[AK4341]
OPERATION OVERVIEW
■
System Clock
The external clocks, which are required to operate the AK4341, are MCLK, LRCK and BICK. The master clock (MCLK)
should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the digital interpolation
filter and the delta-sigma modulator. There are two methods to set MCLK frequency. In Manual Setting Mode (ACKS pin
= “L”, Normal Speed Mode), the frequency of MCLK is set automatically. In Auto Setting Mode (ACKS pin = “H”),
MCLK frequency is detected automatically and then the internal master clock becomes the appropriate frequency (Table
1).
The AK4341 is automatically placed in the power save mode when MCLK stops in the normal operation mode (PDN pin
= “H”), and the analog output becomes the VCOM voltage. After MCLK is input again, the AK4341 is powered up. After
exiting reset at power-up etc., the AK4341 is in the power-down mode until MCLK and LRCK are input.
ACKS pin
H
LRCK
fs
32.0kHz
44.1kHz
48.0kHz
88.2kHz
96.0kHz
176.4kHz
192.0kHz
32.0kHz
44.1kHz
48.0kHz
MCLK (MHz)
256fs
384fs
512fs
-
-
16.3840
-
-
22.5792
-
-
24.5760
22.5792
33.8688
-
24.5760
36.8640
-
-
-
-
-
-
-
8.1920
11.2896
12.2880
12.2880
16.9344
18.4320
16.3840
22.5792
24.5760
128fs
-
-
-
-
-
22.5792
24.5760
-
-
-
192fs
-
-
-
-
-
33.8688
36.8640
-
-
-
768fs
24.5760
33.8688
36.8640
-
-
-
-
24.5760
33.8688
36.8640
1152fs
36.8640
-
-
-
-
-
-
36.8640
-
-
Sampling
Speed
Normal
Double
Quad
Normal
L
Table 1. ACKS pin setting and system clock example
■
Audio Serial Interface Format
The Audio data is shifted in via the SDTI pin using BICK and LRCK inputs. The DIF pin can selects two serial data
modes as shown in Table 2. In all modes the serial data is MSB-first, 2’s compliment format and latched on the rising edge
of BICK.
Mode
0
1
DIF
L
H
SDTI Format
24bit MSB justified
24bit I
2
S
BICK
≥48fs
≥48fs
Figure
Table 2. Audio Data Formats
MS0558-E-01
-9-
2007/03
AKM [ ASAHI KASEI MICROSYSTEMS ]
