ASAHI KASEI
[AK4341]
■ Power-down
The AK4341 is placed in the power-down mode by bringing PDN pin “L” and the analog outputs are VCOM voltage
(VDD). Figure 4 shows an example of the system timing at the power-down and power-up.
PDN
Internal
Normal Operation
Power-down
Normal Operation
State
D/A In
“0” data
(Digital)
GD
GD
(1)
(1)
(3)
(4)
(2)
(3)
D/A Out
(Analog)
Clock In
MCLK, LRCK, BICK
Don’t care
External
MUTE
(5)
Mute ON
Notes:
(1) The analog output corresponding to digital input has the group delay (GD).
(2) Analog outputs are VCOM level (VDD) at the power-down mode.
(3) Click noise occurs at the edge of PDN signal. This noise is output even if “0” data is input.
(4) The external clocks (MCLK, BICK and LRCK) can be stopped in the power-down mode (PDN = “L”).
(5) Please mute the analog output externally if the click noise (3) influences system application.
The timing example is shown in this figure.
Figure 4. Power-down/up Sequence Example
MS0558-E-01
2007/03
- 12 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
