ASAHI KASEI
[AK4309B]
OPERATION OVERVIEW
System Clock
The external clocks which are required to operate the AK4309B are MCLK, LRCK, BICK. The master
clock(MCLK) should be synchronized with LRCK but the phase is not critical. The MCLK is used to operate the
digital interpolation filter and the delta-sigma modulator. The frequency of MCLK is determined by the
sampling rate (LRCK), CKS pin. Table 1 illustrates corresponding clock frequencies. When the 384fs is
selected, the internal master clock becomes 256fs(=384fs*2/3). Refer to Figure 1 .
All external clocks(MCLK,BICK,LRCK) should always be present whenever the AK4309B is in normal
operation mode(RST="H"). If these clocks are not provided, the AK4309B may draw excess current because
the device utilizes dynamic refreshed logic internally. If the external clocks are not present, the AK4309B
should be in the power-down mode(RST ="L"). After exiting reset at power-up etc., the AK4309B is in power-
down mode until MCLK and LRCK are input.
Clock
LRCK (fs)
BICK
MCLK
CKS="L"
CKS="H"
frequency
8k
∼
50kHz
∼
64fs
256fs
384fs
Table 1 . System Clocks
Figure 1 . MCLK divider
Audio Serial Interface Format
Data is shifted in via the SDATA pin using BICK and LRCK inputs. A serial data is MSB-first, 2's compliment
format and is latched by the rising edge of BICK.
Figure 2 . Data Input Timing
0177-E-00
-9-
1997/6
AKM [ ASAHI KASEI MICROSYSTEMS ]
