ASAHI KASEI
[AK4309B]
SWITCHING CHARACTERISTICS
(Ta=25
°C
; AVDD,DVDD=4.5
∼
5.5V; C
L
=20pF)
Parameter
Master Clock Timing
256fs:
Pulse Width Low
Pulse Width High
384fs:
Pulse Width Low
Pulse Width High
Symbol
fCLK
tCLKL
tCLKH
fCLK
tCLKL
tCLKH
fs
Duty
tBCK
tBCKL
tBCKH
tBLR
tLRB
tSDH
tSDS
min
2.048
28
28
3.072
23
23
8
45
312.5
100
100
50
50
50
50
44.1
typ
max
12.8
Unit
MHz
ns
ns
MHz
ns
ns
kHz
kHz
%
ns
ns
ns
ns
ns
ns
ns
ns
19.2
LRCK
Frequency
Duty Cycle
Serial Interface Timing
BICK Period
BICK Pulse Width Low
Pulse Width High
BICK rising to LRCK edge
LRCK Edge to BICK rising
SDATA Hold Time
SDATA Setup Time
Reset Timing
50
55
(Note 11 )
(Note 11 )
RST Pulse Width
(Note 12 )
tRST
150
Notes: 11 . BICK rising edge must not occur at the same time as LRCK edge.
12 . The AK4309B can be reset by bringing RST "L" to "H" only upon power up.
0177-E-00
-7-
1997/6
AKM [ ASAHI KASEI MICROSYSTEMS ]
