ASAHI KASEI
[AK4254]
SWITCHING CHARACTERISTICS
(Ta =-40∼85°C; AVDD=CVDD1=CVDD2=2.7V∼3.6V; C
L
= 20pF)
Parameter
Symbol
Min
typ
max
Units
Control Interface Timing (3-wire Serial mode)
tPDCS
150
ns
PDN “↑” to CSN “↓”
tCCK
200
ns
CCLK Period
tCCKL
80
ns
CCLK Pulse Width Low
tCCKH
80
ns
Pulse Width High
tCDS
40
ns
CDTI Setup Time
tCDH
40
ns
CDTI Hold Time
tCSW
150
ns
CSN “H” Time
tCSS
50
ns
CSN “↓” to CCLK “↑”
tCSH
50
ns
CCLK “↑” to CSN “↑”
Control Interface Timing (I
2
C Bus mode):
SCL Clock Frequency
fSCL
-
400
kHz
PDN “↑” to SDA “↓” @SCL = “H”
tPDSD
1.3
-
μs
Bus Free Time Between Transmissions
tBUF
1.3
-
μs
Start Condition Hold Time
tHD:STA
0.6
-
μs
(Prior to first clock pulse)
Clock Low Time
tLOW
1.3
-
μs
Clock High Time
tHIGH
0.6
-
μs
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
μs
SDA Hold Time from SCL Falling (Note: 10)
tHD:DAT
0
-
μs
SDA Setup Time from SCL Rising
tSU:DAT
0.1
-
μs
Rise Time of Both SDA and SCL Lines
tR
-
0.3
μs
Fall Time of Both SDA and SCL Lines
tF
-
0.3
μs
Setup Time for Stop Condition
tSU:STO
0.6
-
μs
Pulse Width of Spike Noise
tSP
0
50
ns
Suppressed by Input Filter
Capacitive load on bus
Cb
-
400
pF
Reset Timing
tPD
150
ns
PDN Pulse Width
Note: 10. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note: 11. In Serial Control Mode (P/S pin= “L”), it is recommended that the AK4254 is powered up at the PDN pin=“L”.
In Parallel Control Mode, resetting by the PDN pin = “L” is not needed when power up.
Note: 12. I
2
C is a registered trademark of Philips Semiconductors.
MS0586-E-01
-7-
2007/08
AKM [ ASAHI KASEI MICROSYSTEMS ]
