[AK4223]
1. Grounding and Power Supply Decoupling
The AK4223 requires careful attention to power supply and grounding arrangements. AVDD, VVDD and RVDD are
usually supplied from the analog power supply in the system. Alternatively if AVDD, VVDD and RVDD are supplied
separately, AVDD and RVDD must be powered-up at the same time. The power up sequence between AVDD/RVDD and
VVDD is not critical. VSS1 and VSS2 must be connected to the analog ground plane. System analog ground and digital
ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling
capacitors should be as close to the power supply pin of AK4223 as possible.
2. Voltage Reference
VCOM is a signal ground of this chip. An 1μF electrolytic capacitor attached between VCOM and VSS1 eliminates the
effects of high frequency noise. No load current may be drawn from the VCOM pin. To avoid coupling to the AK4223, all
signals and especially clock signals should be kept away as far as possible from the VCOM pin.
3. Notes for Drawing a Board
Analog input and output pins should be as short as possible in order to avoid unwanted coupling into the AK4223. The
unused pins should be open.
MS1251-E-00
24
2010/10
AKM [ ASAHI KASEI MICROSYSTEMS ]
