[AK4145]
DC CHARACTERISTICS
(Ta=-20∼ 85°C; AVDD=TVDD=1.7~3.6V, DVDD=1.7~1.9V)
Parameter
Symbol
min
High-Level Input Voltage
TVDD < 2.7V
VIH
80%TVDD
VIH
70%TVDD
TVDD
≥
2.7V
Low-Level Input Voltage
VIL
-
TVDD < 2.7V
VIL
-
TVDD
≥
2.7V
Low-Level Output Voltage (SDA pin: Iout= 3mA)
VOL
-
Input Leakage Current
Iin
-
typ
-
-
-
-
-
-
Max
-
-
20%TVDD
30%TVDD
0.4
±
10
Units
V
V
V
V
V
μA
SWITCHING CHARACTERISTICS
(Ta=-20∼ 85°C; AVDD=2.7 ~ 3.6V, TVDD=1.7~3.6V, DVDD=1. 7~1.9V)
Parameter
Symbol
min
fCLK
8.192
Master Clock Frequency
dCLK
40
Duty Cycle
LRCK Frequency
fs
32
Duty Cycle
Duty
45
Audio Interface Timing
tBCK
1/128fs
BICK Period
tBCKL
30
BICK Pulse Width Low
tBCKH
30
Pulse Width High
tBLR
20
BICK rising to LRCK Edge
6)
tLRB
20
LRCK Edge to BICK rising
6)
tSDH
20
SDTI Hold Time
tSDS
20
SDTI Setup Time
2
Control Interface Timing (I C Bus)
fSCL
-
SCL Clock Frequency
tBUF
1.3
Bus Free Time Between Transmissions
tHD:STA
0.6
Start Condition Hold Time
(prior to first clock pulse)
tLOW
1.3
Clock Low Time
tHIGH
0.6
Clock High Time
tSU:STA
0.6
Setup Time for Repeated Start Condition
SDA Hold Time from SCL Falling
7)
tHD:DAT
0
SDA Setup Time from SCL Rising
tSU:DAT
0.1
Rise Time of Both SDA and SCL Lines
tR
-
Fall Time of Both SDA and SCL Lines
tF
-
Setup Time for Stop Condition
tSU:STO
0.6
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
-
Capacitive load on bus
Cb
0
Reset Timing
tPD
150
PDN Pulse Width
8)
Note 6. BICK rising edge must not occur at the same time as LRCK edge.
Note 7. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.
Note 8. The AK4145 can be reset by bringing the PDN pin = “L”.
Note 9. I
2
C is a registered trademark of Philips Semiconductors.
typ
max
36.8640
60
48
55
Units
MHz
%
kHz
%
ns
ns
ns
ns
ns
ns
ns
400
-
-
-
-
-
-
-
0.3
0.3
-
50
400
kHz
μs
μs
μs
μs
μs
μs
μs
μs
μs
μs
ns
pF
ns
Rev. 0.3-PB
-6-
2007/12
AKM [ ASAHI KASEI MICROSYSTEMS ]
