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AK4141 参数 Datasheet PDF下载

AK4141图片预览
型号: AK4141
PDF下载: 下载PDF文件 查看货源
内容描述: NICAM / A2 / EIA -J数字立体声解码器 [NICAM/A2/EIA-J Digital Stereo Decoder]
分类和应用: 解码器
文件页数/大小: 19 页 / 277 K
品牌: AKM [ ASAHI KASEI MICROSYSTEMS ]
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[AK4141]  
SWITCHING CHARACTERISTICS (Continued)  
(Ta=-2085°C; AVDD= 3.0~3.6V, DVDD=1.7~1.9V TVDD=1.7~3.6V; GND1=GND2=GND3=GND4=GND5=0V;  
CL=20pF, Cb=400pF(SDA pin))  
Parameter (Note 8)  
Symbol  
min  
typ  
max  
Units  
Audio Interface Timing (Master mode)  
Normal mode (TDM=“0”)  
SCLK Frequency  
fBCK  
dBCK  
tMBLR  
tBSD  
64fs  
50  
Hz  
%
ns  
ns  
SCLK Duty  
SCLK “” to LRCK  
SCLK “” to SDTO  
20  
40  
20  
40  
TDM256 mode (TDM=“1”)  
SCLK Frequency  
SCLK Duty  
SCLK “” to LRCK  
SCLK “” to SDTO  
TDMIN Hold Time  
TDMIN Setup Time  
fBCK  
dBCK  
tMBLR  
tBSD  
tSDH  
tSDS  
256fs  
50  
Hz  
%
ns  
ns  
ns  
ns  
(Note 11)  
12  
20  
10  
12  
20  
10  
Power-Down & Reset Timing  
PDN Pulse Width  
(Note 12)  
(Note 13)  
tPD  
tPDV  
150  
ns  
1/fs  
PDN “” to SDTO valid  
TBD  
Note 7. “L” time at I2S format.  
Note 8. SCLK= SCLK/SCLK4/SCLK5, LRCK= SCLK/LRCK4/LRCK5 unless otherwise specified.  
Note 9. SCLK rising edge must not occur at the same time as LRCK edge.  
Note 10. SCLK= SCLK4/SCLK5, LRCK= LRCK4/LRCK5.  
Note 11. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs.  
Note 12. The AK4141 can be reset by bringing the PDN pin = “L”.  
Note 13. This cycle is the number of LRCK rising edges from the PDN pin = “H”.  
Parameter  
Symbol  
min  
typ  
max  
Units  
Control Interface Timing (I2C Bus):  
SCL Clock Frequency  
fSCL  
tBUF  
tHD:STA  
-
1.3  
0.6  
400  
-
-
kHz  
μs  
μs  
Bus Free Time Between Transmissions  
Start Condition Hold Time  
(prior to first clock pulse)  
Clock Low Time  
Clock High Time  
tLOW  
tHIGH  
tSU:STA  
tHD:DAT  
tSU:DAT  
tR  
1.3  
0.6  
0.6  
0
0.1  
-
-
0.6  
0
-
-
-
0.9  
-
0.3  
0.3  
-
μs  
μs  
μs  
μs  
μs  
μs  
μs  
μs  
ns  
Setup Time for Repeated Start Condition  
SDA Hold Time from SCL Falling (Note 14)  
SDA Setup Time from SCL Rising  
Rise Time of Both SDA and SCL Lines  
Fall Time of Both SDA and SCL Lines  
Setup Time for Stop Condition  
Pulse Width of Spike Noise  
Suppressed by Input Filter  
tF  
tSU:STO  
tSP  
50  
Capacitive load on bus  
Cb  
0
400  
pF  
Note 14. Data must be held for sufficient time to bridge the 300 ns transition time of SCL.  
Note 15. I2C is a registered trademark of Philips Semiconductors.  
Rev. 0.3-PB  
2008/01  
- 12 -