[AK4129]
SYSTEM DESIGN
Figure 48 and Figure 49 shows the system connection diagram. An evaluation board is available which demonstrates
application circuits, the optimum layout, power supply arrangements and measurement results.
• Parallel Control Mode (SPB pin = “L”).
•Synchronous Mode (INAS pin = “L”).
• OMCLK/XTI Input = X’tal mode
• Input PORT: Slave mode, IBICK1 lock mode (64FSI), 24 bit MSB justified
• Output PORT: Slave mode, 24 bit MSB justified
• Dither = OFF, DEM=OFF, PM2/1 pin= “H/L” (6ch original mode)
C1= 0.1μF
C2=10μF
C3=1μF± 30%
3.3V
+
C2
C1
C
+
C2
C1
C3
+
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
IBICK2
IMCLK
ILRCK1
IBICK1
DVDD
VSS2
XTO 48
OMCLK/XTI 47
OLRCK 46
OBICK 45
DVDD 44
VSS4 43
TST7 42
FSO
FSI
64FSO
C1
64FSI
C1
DSP1
DSP2
TST4
SDTI1
SDTI2
SDTO1 41
SDTO2 40
SDTO3 39
ODIF0 38
ODIF1 37
CM0 36
Top View
10 SDTI3
11 IDIF0
12 IDIF1
13 IDIF2
14 ILRCK3
15 IBICK3
16 TST5
CM1 35
CM2 34
TDM 33
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
C1
+
C2
uP
Notes:
- All digital input pins should be not left floating.
- VSS1 -5 must be connected to the same ground plane.
- Connect a 1μF (± 30%; including temperature characteristics) capacitor between the VD18 pin and DVSS. When
this capacitor is polarized, the positive polarity pin should be connected to the VD18 pin.
- Refer to Table 5 for the equivalent series resistance R1 and capacitance C values of the X’tal oscillator.
Figure 48. Typical Connection Diagram (Parallel Control Mode)
MS1173-E-01
2010/09
- 44 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
