[AK4129]
■ Internal Reset Function for Clock Change
Clock change timing is shown in Figure 36 and Figure 37. SDTO is identified as SDTO1, SDTO2 and SDTO3. When
changing the clock, the AK4129 should be reset by the PDN pin in parallel control mode and it should be reset by the PDN
pin or RSTN bit in serial control mode (Figure 36). SDTO means SDTO1-3 in this figure.
External clocks
(Input port
Clocks 1
Clocks 2
Don’t care
or Output port)
PDN pin
max 23ms
(3)
(Internal state) Normal operation Power-down
Note31
Normal operation
Normal data
SDTO
Normal data
SMUTE (Note32,
recommended)
1024/FSO
1024/FSO
0dB
Att.Level
-∞dB
Note 31. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI more than 1024/fs (GD) before
the PDN pin changes to “L”. It makes the data on SDTO remain as “0”.
Note 32. SMUTE can also remove the clicking noise. (Note 31)
Note 33. (3) is the total time of “Internal circuit power-up + FSO/FSI ratio detection + Internal circuit group delay”.
Figure 36. Clock Change Sequence in Parallel Control Mode (SPB pin = “L”)
External clocks
(Input port or Output port)
Clocks 1
Clocks 2
Don’t care
RSTN bit
Reset (Note 28)
(Internal state)
SDTO
Normal operation
Normal data
(4)
Normal operation
Normal data
Note 34
1024/FSO
SMUTE (Note35,recommended)
1024/FSO
0dB
Att.Level
-∞dB
Note 34. The data on SDTO may cause a clicking noise. To prevent this, set “0” to the SDTI from GD before the PDN pin
changes to “L”. It makes the data on SDTO remain as “0”.
Note 35. SMUTE can also remove the clicking noise. (Note 34)
Note 36. The digital block except serial control interface and registers is powered-down. The internal oscillator and
regulator are not powered-down.
Note 37. (4) is the total time of “0.5/FSI+8/FSI(O)+156/FSO” or “1.5/FSI+8/FSI(O)+156/FSO”. (FSI(O) is lower
frequency between FSI and FSO)
Figure 37. Clock Change Sequence in Serial Control Mode (SPB pin = “H”)
MS1173-E-01
2010/09
- 35 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
