[AK4129]
Case 2
External clocks
(Input port)
(No Clock)
(Don’t care)
(Don’t care)
Input Clocks
Input Data
Don’t care
SDTI
Don’t care
Don’t care
External clocks
(Output port)
Output Clocks
PDN
21ms(max)
(2)
Internal Circuit
Power-up Time
ILRCK1-4
Input wait
Normal
operation
Power-down
Power-down
(Internal state)
“0” data
Normal data
Normal data
Normal data
“0” data
“0” data
“0” data
SDTO3
SDTO2
SDTO1
UNLOCK
“0” data
“0” data
Figure 35. System Reset 2
Note 27. SPB, CM2-0, INAS, PM2-1, OBIT1-0, TDM, ODIF1-0, IDIF2-0 and CAD0 pin must be changed when the PDN
pin= “L”.
Note 28. The UNLOCK pin outputs “H” when the PDN pin= “L”. SRC data is output from SDTO1-3 pins, which
corresponds to the each sampling frequency ratio detected SRC, after a rising edge “↑” of PDN if the internal
regulator is in normal operation.
Note 29. (1) is the total time of “Internal circuit power-up + FSO/FSI ratio detection + Clock detection + Internal circuit
group delay”.
Note 30. (2) is the total time of “FSO/FSI ratio detection + Clock detection + Internal circuit group delay”.
MS1173-E-01
2010/09
- 34 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
