ASAHI KASEI
[AK4122]
SYSTEM DESIGN
Figure 29 shows the typical system connection diagram. An evaluation board is available which demonstrates application
circuits, the optimum layout, power supply arrangements and measurement results.
• PORT2, PORT3 : Slave Mode
Digital Supply
3.0 ~ 3.6V
DSP3
uP & DSP
10µ
fso
0.1µ
48 47 46 45 44 43 42 41 40 39 38 37
1
2
3
4
5
6
7
8
9
CDTI
SDTIO 36
BICK2 35
LRCK2 34
MCLK2 33
DVDD 32
DVSS 31
SDTI 30
BICK1 29
LRCK1 28
PDN 27
CDTO
TST1
INT2
DSP2
fsi
Digital Supply
3.0 ~ 3.6V
TST2
TST3
M/S2
0.1µ
10µ
Top View
M/S3
DSP1
fsi
SMUTE
10 TST4
11 TST5
12 FILT
Reset
AVSS 26
R 25
12kΩ
470Ω
2.2µ
2.2n
13 14 15 16 17 18 19 20 21 22 23 24
0.1µ
10µ
Shield
Shield
Shield
Shield
Shield
S/PDIF
sources
Analog Supply
3.0 ~ 3.6V
Note:
- AVSS, BVSS and DVSS of the AK4122 should be distributed separately from the ground of external digital
devices (MPU, DSP etc.).
- All digital input pins should not be left floating.
Figure 29. Typical Connection Diagram
MS0267-E-02
2004/07
- 49 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
