ASAHI KASEI
[AK4121]
SWITCHING CHARACTERISTICS
(Ta=−40∼85°C; VDD=3.0~3.6V; TVDD=3.0~5.5V; C
L
=20pF)
Parameter
Symbol
min
Master Clock Input (MCLK)
Frequency
fCLK
8.192
Duty Cycle
dCLK
40
L/R clock for Input data (ILRCK)
Frequency
fs
8
Duty Cycle
Duty
48
L/R clock for Output data (OLRCK)
Frequency
(Note 9)
fs
32
Duty Cycle
Slave Mode
Duty
48
Master Mode
Duty
Audio Interface Timing
Input
IBICK Period
1/64fs
tBCK
IBICK Pulse Width Low
65
tBCKL
IBICK Pulse Width High
65
tBCKH
ILRCK Edge to IBICK “↑”
(Note 9)
30
tBLR
30
tLRB
BICK “↑” to ILRCK Edge
(Note 9)
30
tSDH
SDTI Hold Time from IBICK “↑”
30
tSDS
SDTI Setup Time to IBICK “↑”
Output (Slave Mode)
OBICK Period
1/64fs
tBCK
OBICK Pulse Width Low
65
tBCKL
OBICK Pulse Width High
65
tBCKH
OLRCK Edge to OBICK “↑”
(Note 9)
30
tBLR
30
tLRB
OBICK “↑” to OLRCK Edge
(Note 9)
tLRS
OLRCK to SDTO (MSB)
tBSD
OBICK “↓” to SDTO
Output (Master Mode)
BICK Frequency
fBCK
BICK Duty
dBCK
tMBLR
−20
BICK “↓” to LRCK
tBSD
−20
BICK “↓” to SDTO
Power-down & Reset Timing
PDN Pulse Width
(Note 10)
tPD
150
Note 8. Min is 8kHz when BYPASS=“H”.
Note 9. BICK rising edge must not occur at the same time as LRCK edge.
Note 10. The AK4121 must be reset by bringing PDN “L” to “H” upon power-up.
typ
-
-
max
36.864
60
96
52
96
52
Units
MHz
%
kHz
%
kHz
%
%
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Hz
%
ns
ns
ns
30
30
64fs
50
20
30
MS0191-E-03
-6-
2004/08
AKM [ ASAHI KASEI MICROSYSTEMS ]
