ASAHI KASEI
[AK4121]
LRCK
0
1
12
13
14
15
16
31
0
1
12
13
14
15
16
31
0
1
BICK
(64fs)
SDTI
16bit
Don’t care
15
0
0
Don’t care
Don’t care
15
0
0
15:MSB, 0:LSB
19 18
19:MSB, 0:LSB
SDTI
20bit
19 18
Don’t care
17 16 15
17 16 15
Lch Data
Rch Data
Figure 1. LSB justified Timing
LRCK
0
1
2
18
19
20
30
31
0
1
2
18
19
20
30
31
0
1
BICK
(64fs)
SDTI
19 18
1
0
Don’t care
19 18
1
0
Don’t care
19 18
20:MSB, 0:LSB
Lch Data
Figure 2. MSB justified Timing
Rch Data
LRCK
0
1
2
3
19
20
21
31
0
1
2
3
19
20
21
31
0
1
BICK
(64fs)
SDTI
0
1
19 18
19:MSB, 0:LSB
Don’t care
19 18
1
0
Don’t care
19
Lch Data
Rch Data
Figure 3. I2S Timing
MS0191-E-03
2004/08
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
