[AK2365]
2) Detail Timing Chart
Write mode
tCSLH
tCSHH
tCSS
CSN
tWH
tWL
SCLK
tDS
tDH
A4
R/W
A5
A3
A0
D7
D6
D1
D0
SDATA
(Input)
High-Z
SDATA
(Output)
Read mode
tCSLH
tCD
tCSS
CSN
tSD
tDD
SCLK
High-Z
R/W
A5
A4
A1
A0
SDATA
(Input)
High-Z
SDATA
(Output)
D7
D6
D1
D0
Rising and falling time
tR
tF
SCLK
VIH
VIL
Parameter
Symbol
tCSS
tDS
Condition
Min.
100
100
100
500
500
100
100
500
Typ.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
CSN setup time
SDATA setup time
SDATA hold time
SCLK high time
SCLK low time
tDH
tWH
tWL
CSN low hold time
CSN high hold time
SDATA Hi-Z setup time
tCSLH
tCSHH
tSD
SCLK to SDATA output delay
time
CSN to SDATA input delay time
tDD
20pF load
20pF load
400
ns
ns
ns
tCD
tR
200
SCLK rising time
SCLK falling time
250
250
tF
Note) Digital input and output timing is relative to 0.5DVDD of rising signal and falling signal.
MS1453-E-01
2012/10
- 10 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
