[AK1542A]
Note 2) The input voltage from the [CPZ] pin is used in the internal circuit. The [CPZ] pin must not be open even when the
fast Lock Up feature is unused.
For the output destination from the [CPZ] pin, see “P.12 Fig.5 Loop Filter Schematic”. The [SWIN] pin could be
open when the fast Lock Up feature is not used.
Note 3) Power down refers to the state where [PDN1]=[PDN2]=”Low” after power-on.
Note 4) TEST1 to 3 must be connected to ground.
AI: Analog input pin
AO: Analog output pin
P: Power supply pin
AIO: Analog I/O pin
G: Ground pin
DI: Digital input pin
DO: Digital output pin
24 23 22 21 20 19
CPVDD
1
2
3
4
5
6
18
17
16
15
14
13
PVDD
RFINP
TEST3
TEST1
RFINN
VREF
DVSS
GPO2
TOP
VIEW
LE
DATA
CLK
7
8
9
10 11 12
Fig. 2 Package Pin Layout
MS1399-E-00
2012/3
- 5 -
AKM [ ASAHI KASEI MICROSYSTEMS ]
