[AK1542A]
Note 2)
The input voltage from the [CPZ] pin is used in the internal circuit. The [CPZ] pin must not be open even when the
fast Lock Up feature is unused.
For the output destination from the [CPZ] pin, see “P.12 Fig.5 Loop Filter Schematic”. The [SWIN] pin could be
open when the fast Lock Up feature is not used.
Note 3)
Note 4)
Power down refers to the state where [PDN1]=[PDN2]=”Low” after power-on.
TEST1 to 3 must be connected to ground.
AI: Analog input pin
DO: Digital output pin
AO: Analog output pin
P: Power supply pin
AIO: Analog I/O pin
G: Ground pin
DI: Digital input pin
CPVSS
PVSS
20
SWIN
24
CPVDD
TEST3
TEST1
LE
DATA
CLK
1
2
3
4
5
6
7
23
22
21
19
18 PVDD
17 RFINP
BIAS
16 RFINN
15 VREF
14 DVSS
13 GPO2
12
CPZ
9
TOP
VIEW
8
10
CP
REFIN
11
TEST2
Fig. 2 Package Pin Layout
MS1399-E-00
-5-
GPO1
PDN2
PDN1
LD
2012/3
AKM [ ASAHI KASEI MICROSYSTEMS ]
